Sony XES-Z50 Service Manual ▷ View online
– 73 –
Pin No.
Pin Name
I/O
Function
79
DIR-ERR
I
PLL unlock error detection signal input from the digital audio interface receiver (IC502)
“H”: error
“H”: error
80
EMP-IN
I
Emphasis detection signal input from the digital signal processor (IC501 CXD2540Q) and
digital audio interface receiver (IC502) “H”: emphasis on
digital audio interface receiver (IC502) “H”: emphasis on
81
VOLMAX
I
Input terminal for the test mode Not used (fixed at “L”)
82
DSP-BUSY
I
Input of busy signal at serial data transfer from the digital signal processor (IC601 CXD2710R)
83
DSP-PLL
I
Not used (fixed at “L”)
84
BU-IN
I
Backup power supply detection signal input terminal (used also to reset standby)
85
DSP-SI
I
Serial data input from the digital signal processor (IC601 CXD2710R)
86
AVSS
—
Ground terminal (for A/D conversion)
87
BUS-ON
I
Bus on/off control signal input from the bus interface (IC306) (for SONY bus) “L”: bus on
With the bus in off status, standby is cancelled by bus on falling edge
With the bus in off status, standby is cancelled by bus on falling edge
88
2711-CE
O
Chip enable signal output to the digital signal processor (IC101, 201 CXD2711Q)
89
FROM-CE2
O
Chip enable signal output to the flash memory (IC401, 402)
90
FROM-CE1
O
Chip enable signal output to the flash memory (IC401, 402)
91
BOOT
I
Input of forced boot mode detection At the reset, if “H” is entered, the boot mode is forcibly
activated
activated
92
VSS
—
Ground terminal
93
LINKOFF1
O
Bus on/off control signal output to the bus interface (IC951) (for SONY bus) “L”: bus on
94
TEND
O
Not used (open)
95
LINKOFF2
O
Bus on/off control signal output for the AUX bus control “L”: bus on
96
LINKOFF3
O
Bus on/off control signal output terminal “L”: bus on Not used (open)
97
VOLCE0
O
Chip enable signal output to the electrical volume (IC1106) (for front speaker)
98
VOLCE1
O
Chip enable signal output to the electrical volume (IC1206) (for rear speaker)
99
VOLCE2
O
Chip enable signal output to the electrical volume (IC1306) (for sub-woofer speaker)
100
A20
O
Address signal output to the flash memory (IC401, 402), and control/data output to the digital
signal processor (IC101, 201 CXD2711Q)
signal processor (IC101, 201 CXD2711Q)
– 74 –
DSP BOARD IC601 CXD2710R (DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Function
1
AMPIN
I
Loop filter amplifier input for the PLL Not used (fixed at “L”)
2
AMPOUT
O
Loop filter amplifier output for the PLL Not used (open)
3
VDD
—
Power supply terminal (+5V)
4
VSS
—
Ground terminal
5
AVSS1
—
Ground terminal (for A/D conversion)
6
VCOC
I
Control signal input for the internal VCO Not used (fixed at “L”)
7
AVDD1
—
Power supply terminal (+5V) (for A/D conversion)
8
VCOOUT
O
Signal output of the internal VCO Not used (open)
9
MCK1 (768FS)
I
Master clock signal (768Fs) input terminal Not used (fixed at “H”)
10
MCK2 (384FS)
I
Master clock signal (384Fs) input terminal
11
MCKOUT
O
Master clock signal output terminal Not used (open)
12
MCKSEL
I
Input terminal for clock signal setting internal VCO or MCK2 (pin !º)
Internal VCO used: “L”, MCK2 (pin !º) used: “H” (fixed at “H”)
Internal VCO used: “L”, MCK2 (pin !º) used: “H” (fixed at “H”)
13
MUTE
I
Mute signal input of the serial interface Not used (fixed at “H”)
14
DIN
I
Program data serial input from the master controller (IC301)
15
VSS
—
Ground terminal
16
SCK
I
Program data transfer clock signal input from the master controller (IC301)
17
CE
I
Program data load input from the master controller (IC301)
18
DOUT
O
Serial data output to the master controller (IC301)
19
BUSY
O
Busy signal at serial data transfer output to the master controller (IC301)
20
RESET
I
Reset signal input from the master controller (IC301) “L”: reset
21 to 27
TEST
I
Not used (fixed at “L”)
28
VDD
—
Power supply terminal (+5V)
29
VSS
—
Ground terminal
30 to 38
TEST
I
Not used (fixed at “L”)
39
M1
O
Parallel data (LSB) output terminal Not used (open)
40
VSS
—
Ground terminal
41
M2
O
42
M3
O
43
M4
O
44
M5
O
45
M6
O
46
M7
O
47
M8
O
48
M9
O
49
M10
O
50
M11
O
51
M12
O
52
M13
O
53
VDD
—
Power supply terminal (+5V)
54
VSS
—
Ground terminal
55
M14
O
Parallel data output terminal Not used (open)
56
M15
O
Parallel data output terminal Not used (open)
57
M16
O
Parallel data (MSB) output terminal Not used (open)
Parallel data output terminal Not used (open)
– 75 –
Pin No.
Pin Name
I/O
Function
58 to 64
TEST
O
Not used (open)
65
VSS
—
Ground terminal
66 to 74
TEST
O
Not used (open)
75
EBDIR
I
Not used (fixed at “L”)
76
UBDIR
I
Not used (fixed at “L”)
77
D.SEL1
I
Input terminal for data output setting serial out or parallel out (fixed at “L”)
78
VDD
—
Power supply terminal (+5V)
79
VSS
—
Ground terminal
80
D.SEL2
I
Input terminal for data output setting serial out or parallel out (fixed at “L”)
81
TEST
I
Not used (fixed at “L”)
82
TEST
I
Not used (fixed at “L”)
83
AVDD2
—
Power supply terminal (+5V) (for A/D conversion)
84
AVSS2
—
Ground terminal (for A/D conversion)
85
AVDD3
—
Power supply terminal (+5V) (for A/D conversion)
86
AVSS3
—
Ground terminal (for A/D conversion)
87
S3OUT
O
Serial data (1 sampling, 2 channel) output for the sub-woofer speaker
88
S2OUT
O
Serial data (1 sampling, 2 channel) output for the rear side speaker
89
S1OUT
O
Serial data (1 sampling, 2 channel) output for the front side speaker
90
VSS
—
Ground terminal
91
S3DI AD
I
Serial data (1 sampling, 2 channel) input for the tuner or external analog audio signal
(ANALOG IN AUX AUDIO)
(ANALOG IN AUX AUDIO)
92
S2DI DIR
I
Serial data (1 sampling, 2 channel) input for the external digital audio signal (DIGITAL IN
AUX AUDIO)
AUX AUDIO)
93
S1DI CD
I
Serial data (1 sampling, 2 channel) input for the CD
94
BCK
I
Bit clock signal (2.8224 MHz) input of the serial in/out data
95
LRCK
I
L/R sampling clock signal (44.1 kHz) input of the serial in/out data
96
LOCK
O
Error signal output of the PLL phase comparator Not used (open)
97
V
O
Divider output for the PLL
98
VAR
I
PLL phase comparator variable input terminal
99
REF
I
PLL phase comparator reference input terminal Not used (fixed at “L”)
100
PD
O
PLL phase comparator charge pump input terminal Not used (open)
– 76 –
pin @™
pin 1
pin !•
“L”
“L”
“H”
Reverse
Stop
“L”
OPEN
“H”
Elevator up
“H”
“L”
“H”
Normal
Stop
“H”
OPEN
“L”
Elevator down
“L”
“H”
“L”
Stop
Reverse
OPEN
“L”
“H”
Disc load
“H”
“H”
“L”
Stop
Normal
OPEN
“H”
“L”
Disc save
7-2. IC201 (BA6247FP-Y) MOTOR DRIVER IC OPERATION
(DRIVER BOARD)
The elevator up/down motor connected between pin @™ and pin !• of IC201 is as M501, and the disc load/save motor connected
between pin 1 and pin !• of IC201 is as M502.
When the IC port logic is pin @™ > pin !•, pin 1 > pin !•, the rotating direction of M501 and M502 becomes normal.
between pin 1 and pin !• of IC201 is as M502.
When the IC port logic is pin @™ > pin !•, pin 1 > pin !•, the rotating direction of M501 and M502 becomes normal.
ROTATION TRUTH TABLE
1 When MB=MC: both M501 and M502 are stop. (MA value is free.)
2 When MB
2 When MB
≠
MC:
Operation
MA
(pin 8)
MC
(pin 6)
M501
M502
Disc load/save
Elevator up/down
M502
(1–18)
M501
(22–18)
!•
@™
!•
1
Pin of IC301
Rotating direction
of motor
Pin of IC201
MB
(pin 7)
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