Sharp XG-NV1E (serv.man18) Service Manual ▷ View online
XG-NV1U
53
REGISTER FUNCTION
SUB
ADD
(1)
DATA BYTE
(2)
D7
D6
D5
D4
D3
D2
D1
D0
Luminance contrast
13
159
158
157
156
155
154
153
152
CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0
HSY begin 60 Hz
14
167
166
165
164
163
162
161
160
HS6B7
HS6B6
HS6B5
HS6B4
HS6B3
HS6B2
HS6B1
HS6B0
HSY stop 60 Hz
15
175
174
173
172
171
170
169
168
HS6S7
HS6S6
HS6S5
HS6S4
HS6S3
HS6S2
HS6S1
HS6S0
HCL begin 60 Hz
16
183
182
181
180
179
178
177
176
HC6B7
HC6B6
HC6B5
HC6B4
HC6B3
HC6B2
HC6B1
HC6B0
HCL stop 60 Hz
17
191
190
189
188
187
186
185
184
HC6S7
HC6S6
HC6S5
HC6S4
HC6S3
HC6S2
HC6S1
HC6S0
HSY after PHI1 60 Hz
18
199
198
197
196
195
194
193
192
HP617
HP616
HP615
HP614
HP613
HP612
HP611
HP610
Luminance brightness
19
207
206
205
204
203
202
201
200
BRIG7
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
DUAD slave receiver (SU 20H to 32H)
Analog control #1
20
007
006
005
004
003
002
001
000
AIND4
AIND3
AIND2
FUSE1
FUSE0
AINS4
AINS3
AINS2
Analog control #2
21
015
014
013
012
011
010
009
008
BVCO
MS34
MX241
MX240
MS24
REFS4
REFS3
REFS2
Mixer control #1
22
023
022
021
020
019
018
017
016
GACO1 GACO0
CSEL
YSEL
MUYC
CLTS
MX341
MX340
Clamping level control 21
23
031
030
029
028
027
026
025
024
CLL217 CLL216 CLL215 CLL214 CLL213 CLL212 CLL211 CLL210
Clamping level control 22
24
039
038
037
036
035
034
033
032
CLL227 CLL226 CLL225 CLL224 CLL223 CLL222 CLL221 CLL220
Clamping level control 31
25
047
046
045
044
043
042
041
040
CLL317 CLL316 CLL315 CLL314 CLL313 CLL312 CLL311 CLL310
Clamping level control 32
26
055
054
053
052
051
050
049
048
CLL327 CLL326 CLL325 CLL324 CLL323 CLL322 CLL321 CLL320
Gain control analog #1
27
063
062
061
060
059
058
057
056
HOLD
GASL
GAI25
GAI24
GAI23
GAI22
GAI21
GAI20
White peak control
28
071
070
069
068
067
066
065
064
WIPE7
WIPE6
WIPE5
WIPE4
WIPE3
WIPE2
WIPE1
WIPE0
Sync bottom control
29
079
078
077
076
075
074
073
072
SBOT7
SBOT6
SBOT5
SBOT4
SBOT3
SBOT2
SBOT1
SBOT0
Gain control analog #2
2A
087
086
085
084
083
082
081
080
IWIP1
IWIP0
GAI35
GAI34
GAI33
GAI32
GAI31
GAI30
Gain control analog #3
2B
095
094
093
092
091
090
089
088
IGAI1
IGAI0
GAI45
GAI44
GAI43
GAI42
GAI41
GAI40
Mixer control #2
2C
103
102
101
100
099
098
097
096
CLS4
XXX
CLS3
CLS2
XXX
XXX
TWO3
TWO2
Integration value gain
2D
111
110
109
108
107
106
105
104
IVAL7
IVAL6
IVAL5
IVAL4
IVAL3
IVAL2
IVAL1
IVAL0
XG-NV1U
54
REGISTER FUNCTION
SUB
ADD
(1)
DATA BYTE
(2)
D7
D6
D5
D4
D3
D2
D1
D0
Vertical blanking pulse set
2E
119
118
117
116
115
114
113
112
VBPS7
VBPS6
VBPS5
VBPS4
VBPS3
VBPS2
VBPS1
VBPS0
Vertical blanking pulse reset
2F
127
126
125
124
123
122
121
120
VBPR7
VBPR6
VBPR5
VBPR4
VBPR3
VBPR2
VBPR1
VBPR0
ADC
S
gain control
30
135
134
133
132
131
130
129
128
XXX
WISL
GAS3
GAD31
GAD30
GAS2
GAD21
GAD20
Mixer control #3
31
143
142
141
140
139
138
(3)
137
136
AOSL1
AOSL0
WIRS
WRSE
SQPB
AFCCS
VBLKA
PULIO
Integration value white peak
32
151
150
149
148
147
146
145
144
WVAL7
WVAL6
WVAL5
WVAL4
WVAL3
WVAL2
WVAL1
WVAL0
Mixer control #4
33
159
158
157
156
155
154
153
152
OFTS
XXX
CHSB
XXX
CAD3
CAD2
XXX
XXX
Gain update level
34
167
166
165
164
163
162
161
160
MUD2
MUD1
GUDL5
GUDL4 GUDL3 GUDL2 GUDL1
GUDL0
VERSION STATUS BYTE
D7
D6
D5
D4
D3
D2
D1
D0
ID7 TO ID0; note 1
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Note:
1. ID7 to ID0 indicates the version number of the IC, for example SAA7110A V1=01H.
8-6-3. OCF1 Transmitter :
Byte number 1 (transmitted if SSTB=1)
Slave address: 10011101b, 9DH (SA=0) and 10011111b, 9FH (SA=1)
STATUS BYTE FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
See Table 10 for explanation of bits
STTC
HLCK
FIDT
GLIM
XXX
WIPA
ALTD
CODE
Notes:
1. Subaddresses to be reset : 0D to 7HD, 0E and 31 to 00H after RESET=0 (CGCE=0) or power-on (CGCE=1).
2. All reserved XXX-bits must be set to LOW, XX-bit is don't care.
3. AFCCS bit does not exist in SAA7110A due to advanced anti-alias filter characteristic, don't care (XX).
2. All reserved XXX-bits must be set to LOW, XX-bit is don't care.
3. AFCCS bit does not exist in SAA7110A due to advanced anti-alias filter characteristic, don't care (XX).
8-6-2. OCF1 Transmitter :
Byte number 0 (transmitted if SSTB=0 or after RESET has been 0)
Slave address: 10011101b, 9DH (SA=0) and 10011111b, 9FH (SA=1)
XG-NV1U
55
Explanation of bits shown in 8-6-3.
BIT
DESCRIPTION
STTC
Status bit for horizontal time constant : LOW = TV time constant : HIGH = VCR time constant.
HLCK
Status bit for locked horizontal frequency : LOW = locked : HIGH = unlocked.
FIDT
Identification bit for detected field frequency : LOW = 50 Hz : HIGH = 60 Hz.
GLIM
Gain value for active luminance is limited (maximum or minimum), active HIGH.
XXX
reserved
WIPA
White peak loop is activated, active HIGH.
ALTO
Status HIGH : line alternating colour burst has been detected (PAL or SECAM).
CODE
Status HIGH : any colour signal has been detected.
8-7. I
2
C-Bus Detall
The I
2
C-bus receiver slave address is 9CH/9EH.
DMSD-SQP slave receiver (SU 00H to 19H).
8-7-1. Subaddress 00 (DATA BYTE 007 to 000)
Increment delay IDEL
-1
-4
1
1
1
1
1
1
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
-195
-780
0
0
1
1
1
1
0
1
max, value for 60 Hz
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
-236
-944
0
0
0
1
0
1
0
0
max,value for 50 Hz
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
-256
-1024
0
0
0
0
0
0
0
0
outside central counter
(2)
DECIMAL
DELAY TIME
MULTIPLIER
(STEP SIZE = 4/LLC)
CONTROL BITS
(1)
IDEL7
IDEL6
IDEL5
IDEL4
IDEL3
ODEL2
IDEL1
IDEL0
Notes:
1. A sigh bit, designated A08 and internally set to HIGH, indicates are always negative.
2. Thwe horizontal PLL does not operate in this condition. The system clock frequency is to a value fixed by
2. Thwe horizontal PLL does not operate in this condition. The system clock frequency is to a value fixed by
the last update and is within ±7.1% of the nominal frequency.
DECIMAL
DELAY TIME
MULTIPLIER
(STEP SIZE = 2/LLC)
CONTROL BITS
HSYB7 HSYB6 HSYB5 HSYB4 HSYB3 HSYB2 HSYB1 HSYB0
8-7-2. Subaddress 01 (DATA BYTE 015 to 008)
Horizontal synchronization begin 50 Hz (HSYB)
+191
-382
1
0
1
1
1
1
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
-64
+128
1
1
0
0
0
0
0
0
XG-NV1U
56
DECIMAL
DELAY TIME
MULTIPLIER
(STEP SIZE = 2/LLC)
CONTROL BITS
HSYS7 HSYS6 HSYS5 HSYS4 HSYS3 HSYS2 HSYS1 HSYS0
8-7-3. Subaddress 02 (DATA BYTE 023 to 016)
Horizontal synchronization stop 50 Hz (HSYS)
+191
-382
1
0
1
1
1
1
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
-64
+128
1
1
0
0
0
0
0
0
DECIMAL
DELAY TIME
MULTIPLIER
(STEP SIZE = 2/LLC)
CONTROL BITS
HCLB7 HCLB6 HCLB5 HCLB4 HCLB3 HCLB2 HCLB1 HCLB0
8-7-4. Subaddress 03 (DATA BYTE 031 to 024)
Horizontal clamping begin 50 Hz (HCLB)
+127
-254
0
1
1
1
1
1
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
-128
+256
1
0
0
0
0
0
0
0
DECIMAL
DELAY TIME
MULTIPLIER
(STEP SIZE = 2/LLC)
CONTROL BITS
HCLS7 HCLS6 HCLS5 HCLS4 HCLS3 HCLS2 HCLS1 HCLS0
8-7-5. Subaddress 04 (DATA BYTE 039 to 032)
Horizontal clamping stop 50 Hz (HCLS)
+127
-254
0
1
1
1
1
1
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
-128
+256
1
0
0
0
0
0
0
0
8-7-6. Subaddress 05 (DATA BYTE 047 to 040)
Horizontal synchronization start after PHI1 50 Hz (HPHI)
DECIMAL
DELAY TIME
MULTIPLIER
(STEP SIZE = 4/LLC)
CONTROL BITS
HPHI7
HPHI6
HPHI5
HPHI4
HPHI3
HPHI2
HPHI1
HPHI0
+127
0
1
1
1
1
1
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
+118
0
1
1
1
0
1
1
0
+117
0
1
1
1
0
1
0
1
-118
1
0
0
0
1
0
1
0
-119
1
0
0
0
1
0
0
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
-128
1
0
0
0
0
0
0
0
forbidden;
outside available central
counter range
outside available central
counter range
-32µs
(max. negative value)
(max. negative value)
+31.7µs
(max. positive value)
(max. positive value)
forbidden;
outside available central
counter range
outside available central
counter range
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