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The 16-bit YUV-bus transfers digital data from the output interfaces to a feature box, or a field memory.

The output are controlled by an output enable chain (FEIN on pin 63).

The YUV data rate equals LLC2. Timing is acheived by marking each second positive rising edge of the clock LLC
in conjunction with CREF (clock reference).

The output signals Y7 to Yo are the bits of the digital luminance signal. The output signals UV7 to UV0 are the bits
of multiplexed colour difference signals (B-Y) and (R-Y). The frame in the format tables is the time, required to
transfer a full set of samples. In the event of 4:2:2 format two luminance samples are transmitted in comparison to
one U and one V sample within the frame.
The time frames are controlled by the HREF signal.

Fast enable is achieved by setting input FEIN to LOW. The signal is used to control fast switching on the digital
YUV-bus. HIGH on this pin forces the Y and UV outputs to a high-impedance state.

The pre-filtered luminance signal is fed to the synchronization stage. It's bandwidth is reduced to 1 MHz in a low-
pass filter.

The synchronization pulses are sliced and fed to the phase detectors where they are compared with the sub-
divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations.
Adjustable output signals HCL and HSY are generated in accordance with analog front end requirements. The
output signals HS, VS, and PLIN are locked to the timing reference, guaranteed between the input signal and the
HREF signal, as further improvements to the circuit may change the total processing delay. It is therefore not
recommended to use them for applications which require absolute timing accuracy to the input signals. The loop
filter signal drives an oscillator to generate the line frequency control signal LFCO.

The internal CGC generates all clock signals required for the one chip front-end. The output signal LFCO is a
digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency (7.38 MHz
= 472 x fn in 50 Hz systems and 6.14 MHz = 360 x fn in 60Hz systems). Internally the LFCO signal is multiplied by
a factor of 2 or 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the
LLC and LLC2 output clock signals. The rectangular output clocks have a 50% duty factor.

Power-on reset is activated at power-on (using only internal CGC), when the supply voltage decreases below 3.5 V.
The indicator RESET is LOW for a time. THe RESET signal can be applied to reset other circuits of the digital TV
system.

The real time control and status output signal contains serial information about actual system clock, subcarrier
frequency and PAL/SECAM sequence. The signal can be used for various applications in external circuits, forexample,
in a digital encoder to achieve clean encoding.

SOURCE

SWITCH

A142

A141

11

13

20, 16, 12

10, 14, 10

V

DDA2 

to V

DDA4

V

SSA2 

to V

SSA4

AINS4

AIND4

SOURCE

SWITCH

A132

A131

15

17

AINS3

AIND3

SOURCE

SWITCH

A122

A121

i.c.

i.c.

i.c.

9

8

7

19

21

V

SS (S)

22

AINS2

AIND2

ANALOG

CONTROL

WISL

IVAL

WVAL

GUDL

WIRS

GAS2

GAS3

GAD2

GAD3

WRSE

YSEL

CSEL

TWO2

TWO3

CLTS

CLS2

CLS3

CLS4

CLL2n

CLL3n

WIPA

GLIM

IIOLD

WIPE

SDOT

GASL

VBPS

VBPR

VBCO

MUYC

MS24

MS34

MX24

MX34

MUD1

MUD2

GACO

GAI2

GAI3

GAI4

IWIP

IGAI

CLAMP

CIRCUIT

REFS4

CLAMP

CIRCUIT

REFS3

CLAMP

CIRCUIT

ANALOG

AMPLIFIER

ANALOG

AMPLIFIER

ANALOG

AMPLIFIER

ANTI-ALIAS

FILTER

ANTI-ALIAS

FILTER

ANTI-ALIAS

FILTER

BYPASS

SWITCH

BYPASS

SWITCH

BYPASS

SWITCH

FAST

SWITCH

ADDER

FAST

SWITCH

ADDER

SOURCE

SWITCH

SOURCE

SWITCH

SOURCE

SWITCH

SOURCE

SWITCH

SOURCE

SWITCH

SOURCE

SWITCH

TEST

SELECTOR

ADC

ADC

REFS2

FUSE

AOSL

AOUT

23

FUSE

FUSE

A

B

BYPS

CHRS

CODE

SXCR

SEQA

ALTD

SEQA

HUEC

COLO

SECS

SESE

PLSE

CHCV

CKTQ

CKTS

LFIS

V

DD

68, 52, 44,

34, 27

V

SS

67, 51, 43,

35, 28

SOPB

HRMV

HRFS

OFTS

CHSD

OEYC

OEHV

FEN1

(MUXC)

UV7 to UV0

Y7 to Y0

HREF

42

63

55 to

62

45 to 50,

53, 54

BRIG

CONT

SATN

INPUT

INTERFACE

CHROMINANCE

BANDPASS

CHROMINANCE CIRCUIT

QUADRATURE

DEMODULATOR

LOW PASS

GAIN

CONTROL

LOW PASS

OUT PUT

FORMATTER

AND INTERFACE

DISCRETE TIME

OSCILLATOR

(DT01)

AND DIVIDER

SEQUENCE

PROCESSON

LOOP FITER

P12

CLOCH FILTER

DIFFERENTIATOR

STANDARD

CONTROL

DE EMPHASIS

LOOP FILTER

P11

BURST GATE

ACCUMULATOR

PHASE

DEMODULATOR

AMPLITUDE

DETECTOR

COMB FILTERS

AND SECAM

RECOMBINATION

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

A

B

C

D

PREFILTER

CHROMINANCE

TRAP

PREFILTER

SYNC

I

2

C DUS

INTERFACE

SYNC

SLICER

PHASE

DETECTOR

FINE

COUNTER

VERTICAL

PROCESSOR

PHASE

DETECTOR

COARSE

LOOP FILTER

2

TEST

CONTROL

BLOCK

AP

SP

PREF

BYPS

LUMINANCE CIRCUIT

SYNCHRONIZATION CIRCUIT

VARIABLE

BANDPASS

FILTER

BFBY

PREF

BPSS

HLCK

VTRC

VNOI

FSEI

AUDF

HSGB

HSGS

HCGB

HCGS

PULIO

OEHV

SCEN

IDEL

HSYU

HSYS

HCLB

HCLS

HPBI

HPGI

V

SSA0

VS

ODD (VL)

RICO

HS

HCL

SA

SCL

SDA

CGCE

V

DDA0

HSY

PLIN (RL)

25

24

33

41

3

39

38
37

36

456

40

HLCK

STTC

VBLKA

SS1D

GPPSW

I

2

C BUS

CONTROL

FIDT

HPLL

HLCK

CORING

MATCHING

AMPLIFIER

COR1

WEIGHTING

AND

ADDING STAGE

APER

VARIABLE

DELAY

POWER ON

CONTROL

LINE LOCKED

CLOCK

GENERATOR

DELAY

ADJUSTMENT

CRYSTAL

CLOCK

GENERATOR

DISCRETE TIME

OSCILLATOR

(DTO2)

DAC4

DAC6

CLOCK

GENERATION

CIRCUIT

YDEL

CLOCK (3 to 0)

RESET

32

CREF

31

LLC

29

LLC2

30

XTAL1

66

XTAL0

65

LIC0

26

2

GPSW

(VBLK)

64

1

D

C