Sharp XG-NV1E (serv.man18) Service Manual ▷ View online
XG-NV1U
37
7-1. Video Unit General Layout
8
8
8
8
X’ tal
26.8MHz
Audio input (L)
Audio input (R)
Composite
video input
S video input
Audio output (L)
Audio output (R)
+6V input
+5V
+3.3V
5V-3V level switching
74LVT24a4A
(Phillips)
Y output
(8 bits)
Video decoder
SAA7110(A)
(Phillips)
3.3V regulator
MM1180
(Mitsumi)
5V-3V level switching
74LVT244A
(Phillips)
5V-3V level switching
74LVT125
(Phillips)
5V regulator
PQ05TZ51
(SHARP)
U/V output
(8 bits)
I
2
C
(SCL, SDA)
Clock output
Figure 7-1.
XG-NV1U
38
8. ONE CHIO FRONT -END 1 (OCF1) (IC6001: SAA7110 (A))
8-1. Features
»
Two 8-bit video CMOS analog-to-digital converters
»
Luminance and chrominance signal processing for PAL B/G, NTSC M and SECAM
»
Full range HUE control
»
Automatic detection of 50/60 Hz field frequency, and automatic switching between standards PAL and NTSC, SECAM
forceable
forceable
»
Horizontal and vertical sync detection for all standards
»
Cross-colour reduction by chrominance comb filtering for NTSC or special cross-colour cancellation for SECAM
»
UV signal delay lines for PAL to correct chrominance phase errors
»
The YUV-bus supports a data rate of:
-780 x fn=12.2727 MHz for 60 Hz (NTSC)
-944 x fn=14.75 MHz for 50 Hz (PAL/SECAM)
-780 x fn=12.2727 MHz for 60 Hz (NTSC)
-944 x fn=14.75 MHz for 50 Hz (PAL/SECAM)
»
Square pixel format with 768/640 active samples perline on the YUV-bus
»
CCIR 601 level compatible
»
4:2:2 YUV output formats in 8-bit resolution
»
Requires only one crystal (26.8 MHz) for all standards
»
Real time status information output (RTCO)
»
Brightness Cotrast Saturation (BCS) control for the YUV-bus
»
Power-on control
»
I
2
C-bus controlled
XG-NV1U
39
8-2. Block Diagram
ANALOG
PROCESSING
CON
AD2
AD3
ANALOG
CONTROL
TEST
CONTROL
BLOCK
Y/CVBS
Y
Y
LUMINANCE
CIRCUIT
CHROMINANCE
CIRCUIT
C/CVBS
BYPASS
I
2
C-BUS
INTERFACE
I
2
C-BUS
CONTROL
SA
SDA
SCL
GPSW
(VBLK)
UV7
to
UV0
55 to 62
45 to 50,
53,54
Y7 to Y0
HREF
XTALO
XTALI
LLC2
CREF
LLC
RESET
FEIN
(MUXC)
BRIGHTNESS
CONRAST
SATURATION
CONTROL
AND
OUTPUT
FORMATTER
CLOCK
GENERATION
CIRCUIT
POWER-ON
CONTROL
63
42
65
66
30
31
29
32
4
5
6
64
26
33
25
24
3
39
40
36
37
38
41
VS
SS
DD
HS
HSY
HCL
PLIN(HL)
RTCO
ODD(VL)
V
V
DDAO
CGCE
LFCO
SSAO
SAA7110
SAA7110A
CLOCKS
Y
UV
8
SYNCHRONIZATION
CIRCUIT
SP
AP
SS(S)
V
V
68,52,44,
34,27
67,51,43,
35,28
V
DDA2
to V
DDA4
V
SSA2
to V
SSA4
18,14,10
7,8,9
20,16,12
22
2
1
I.C.
AI21
AI22
AI31
AI32
AI41
AI42
AOUT
23
11
13
15
17
19
21
Figure 8-1.
XG-NV1U
40
8-3. Pinning
SYMBOL
PIN
SP
1
AP
2
RTCO
3
SA
4
SDA
5
SCL
6
i.c.
7
i.c.
8
i.c.
9
V
SSA4
10
AI42
11
V
DDA4
12
AI41
13
V
SSA3
14
AI32
15
V
DDA3
16
AI31
17
V
SSA2
18
AI22
19
V
DDA2
20
AI21
21
V
SS(S)
22
AOUT
23
V
DDA0
24
V
SSA0
25
LFCO
26
V
DD
27
V
SS
28
LLC
29
LLC2
30
CREF
31
DESCRIPTION
test pin input ; (shift pin) connect to ground for normal operation
test pin input ; (action pin) connect to ground for normal operation
Real Time Control Output. This pin is used to fit serially the increments of the HPLL and
FSC-PLL and information of the PAL or SECAM sequence.
I
2
C-bus slave address select input. LOW: slave address = 9CH for write, 9DH for read;
HIGH = 9DH for write, 9FH for read.
I
2
C-bus serial data input/output
I
2
C-bus serial clock input
reserved pin; do not connect
reserved pin; do not connect
reserved pin; do not connect
ground for analog input 4
analog input 42
supply voltage (+5V) for analog input 4
analog input 41
ground for analog input 3
analog input 32
supply voltage (+5V) for analog input 3
analog input 31
ground for analog input 2
analog input 22
supply voltage (+5V) for analog input 2
analog input 21
substrate ground
analog test output; do not connect
supply voltage (+5V) for intrenal CGC (Clock Generation Circuit)
ground for internal CGC
Line Frequency Control output; this is the analog clock control signal driving the external
CGC. The frequency is a multiple of the actual line frequency (nominally 7.375/6.13636
MHz). The signal has a triangu; ar form with 4-bit accuracy.
supply voltage (+5V)
ground
Line-Locked Clock input/output (CGCE=1, output; CGCE=0, input). This is the system
clock, its frequency is 1888 x fn for 50 Hz/625 lines per field systems and 1560 x fn for
60Hz/525 lines per field systems; or variable input clock up to 32 MHz in input mode.
Line-Locked Clock 1/2 output; f
LLC2
=0.5 x f
LLC
(CGCE=1, output; CGCE=0, high imped-
ance).
Clock reference input/output (CGCE=1, output; CGCE=0, input). This is a clock qualifier
signal distributed by the internal or an external clock generator circuit (CGC). Using CREF all
interfaces on the YUV-bus are able to generate a bus timing with identical phase.
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