Sharp XG-NV1E (serv.man18) Service Manual ▷ View online
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3. OUTPUT CIRCUIT
3-1. 6-ch Divider Drive Circuit
3-1-1. Behavior outline
Fig. 3-1. shows a block circuit of the 6-channel divider drive circuit. The behavior of each component is discussed
below.
below.
A1
A2
A3
A4
A5
A6
O1
O2
O3
O4
O5
O6
AGC
amplifier
Bias control
circuit
LCD
S/H circuit
S/H circuit
Error amplifier
circuit
MUX
Figure 3-1. 6-channel divider drive circuit block diagram
1. AGC amplifier
The input signal is line-inverted and amplitude-controlled at once.
2. Bias control circuit
The 100% white level voltage is controlled here.
3. MUX
One of the 6 channels is selected and its output is fed to the error amplifier circuit.
4. Error amplifier circuit
The output voltage and the reference voltage are compared, and their error is corrected with an output voltage.
5. S/H circuit
The gate pulse gets to the high or low level when the reference signal is given that is contained in the video signal.
With the gate pulse at high, the sample mode is brought about. With the gate pulse at low, the hold modeis called
up and the error amplifier circuit’s output voltage is held.
With the gate pulse at high, the sample mode is brought about. With the gate pulse at low, the hold modeis called
up and the error amplifier circuit’s output voltage is held.
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Figure 3-3. AGC amplifier
characteristics
Figure 3-2. AGC amplifier
3-1-2. AGC amplifier
The video signal, divided into 6 channels, is line-inverted and amplitude-controlled at the same time by the AGC
amplifier (NJM1496V), as shown in
amplifier (NJM1496V), as shown in
Figure 3-2.. The video signal being fed to the AGC amplifier has an amplitude
of 1 Vp-p, and the 100% white level at 0V and the black level at +1 V. The input signal is given out of pin (6) with the
amplitude proportional to (voltage at pin (8) - voltage at pin (10)), as shown in
amplitude proportional to (voltage at pin (8) - voltage at pin (10)), as shown in
Figure 3-3.. On the other hand, the
output from pin (12) comes out with the polarity inverted from that at pin (6). The VB voltage, as shown in
Fig. 3-2,
is an amplitude control voltage for all the channels. This signal is polarity-inverted line by line with the +5 V position
at the center. Those polarity and amplitude determine the polarity and amplitude of the output. The VBC voltage,
also shown in
at the center. Those polarity and amplitude determine the polarity and amplitude of the output. The VBC voltage,
also shown in
Figure 3-2., is used to correct an amplitude error between the channels. This signal is given out of
the amplitude correction S/H circuit.
–
+
R2
Vo
R3
R4
+12V
Vw
Vwc
R2
Q2
R1
R1
I
Q1
–Vs
+Vs
Re
Vr
–5V
Figure 3-4. Bias control circuit
3-1-3. Bias control circuit
The output of the AGC amplifier has its DC bias still
unregulated. The bias control circuit is intended to
regulate the bias. In the circuit shown in
unregulated. The bias control circuit is intended to
regulate the bias. In the circuit shown in
Figure 3-4.,
the output voltage Vo becomes
(2 x R2 x Vs/R1) - I x R2.
This means that the output bias depends on the collector
current of Q1. This collector current I is determined by
the following voltages: video center control voltage Vr,
white level polarity inversion voltage Vw (in setting line
period) and channel-to-channel white level correction
voltage Vwc.
Thus the following equation is obtained.
I = {(R4 x Vw + R3 x Vwc) / (R3 + R4) - Vr} / Re
(2 x R2 x Vs/R1) - I x R2.
This means that the output bias depends on the collector
current of Q1. This collector current I is determined by
the following voltages: video center control voltage Vr,
white level polarity inversion voltage Vw (in setting line
period) and channel-to-channel white level correction
voltage Vwc.
Thus the following equation is obtained.
I = {(R4 x Vw + R3 x Vwc) / (R3 + R4) - Vr} / Re
1
2
3
4
5
6
7
14
13
–5V
12
11
10
9
8
NJM1496V
VB
VBC
+2.5V
+12V
Vout-n
Vout-p
Vin
Vout
V
8
–V
0
w
6
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3-1-4. MUX
The NJU4051V multiplexer is used in the unit.
Figure 3-5. and 3-6. show the pin connections and the truth table,
respectively. The SEL0, SEL1 and SEL2 signals are used to select channels. Because Vcc is +12 V, the logic’s high
level is set at +12 V.
level is set at +12 V.
Figure 3-7. Error amplifier circuit
–
+
LIMITTER
Vo
–Vw
–Vb
–Vc
3-1-5. Error amplifier circuit
Figure 3-7. shows the error amplifier circuit. For the signal of a selected channel, the white level voltage, black level
voltage and video center voltage are all polarity-inverted into -Vw, -Vb and -Vc, which are all added together. The
gain of this error amplifier circuit becomes only stable when the video output’s white level reference voltage gets
equal to Vw+Vc and its black level reference voltage equal to Vw+Vc+Vb. This is because the gain is close to the
operational amplifier’s open loop gain and also very high.
voltage and video center voltage are all polarity-inverted into -Vw, -Vb and -Vc, which are all added together. The
gain of this error amplifier circuit becomes only stable when the video output’s white level reference voltage gets
equal to Vw+Vc and its black level reference voltage equal to Vw+Vc+Vb. This is because the gain is close to the
operational amplifier’s open loop gain and also very high.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NJM14051V
+12V
O5
C0
O6
O4
O1
O2
O3
INH
Vee GND
SEL2
SEL1
SEL0
Vcc
Figure 3-5. Multiplexer
INH
SEL0
SEL1
SEL2
ON channel
0
0
0
0
O1
0
1
0
0
O2
0
0
1
0
O3
0
1
1
0
O4
0
0
0
1
O5
0
1
0
1
O6
1
X
X
X
NONW
Figure 3-6. Truth table
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3-1-6. S/H (Sample/Hold) circuit
The block diagram in
Figure 3-8. refers to the sample/hold circuit for one of the 6 channels. Refer back to the 6-
channel divider drive circuit in
Figure 3-1.. When the REFW signal (white level correction gate pulse) gets to the
high level, the SW1 turns on to form the loop (1). This loop gets stable when the output signal’s white level reference
voltage becomes equal to the addition of the white level setting voltage and video center voltage. The then white
level correction voltage is charged to the Chw. When the REFW signal gets to the low level, the SW1 turns off and
held in this state. Similarly when the REFBK signal (black level correction gate pulse) gets to the high level, the
SW2 turns on to form the loop (2). This loop gets stable when the output’s black level reference voltage becomes
equal to the addition of the white level setting voltage, black level setting voltage and video center voltage. The then
black level correction voltage is charged to the Chb and held at this level when the REFBK signal level is low.
voltage becomes equal to the addition of the white level setting voltage and video center voltage. The then white
level correction voltage is charged to the Chw. When the REFW signal gets to the low level, the SW1 turns off and
held in this state. Similarly when the REFBK signal (black level correction gate pulse) gets to the high level, the
SW2 turns on to form the loop (2). This loop gets stable when the output’s black level reference voltage becomes
equal to the addition of the white level setting voltage, black level setting voltage and video center voltage. The then
black level correction voltage is charged to the Chb and held at this level when the REFBK signal level is low.
Vc
0V
0V
0V
0V
Vb
Vw
Vb
Vw
1V
Figure 3-9. Waveforms
Vin
: Input signal
Vo
: Video output
FRP 1 : Polarity-inverting signal
FRP 2 : FRP1 inversion
Vb
: Black level setting voltage
Vw
: White level setting voltage
Figure 3-8. S/H circuit
AGC
+
+
+
+
+
–1
–1
+
–
+
–
1
2
Vin
Vw
Vb
Chw
Chb
REFBK
REFW
Vo
–Vc
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