Sharp XG-NV1E (serv.man18) Service Manual ▷ View online
XG-NV1U
17
2-3. SVP (Signal Video Processor)
2-3-1. SVP (Signal Video Processor) layout
DO23~DO0
SRCK,RSTRH,RE
MUX
SWCK,RSTWH,WE
DI31~DI0
DI35~32(kvf) :
Conversion coefficient
Conversion coefficient
DIR: 960 x 32 bits
YUV mode
processing circuit
RGB mode
processing circuit
DOR: 960 x 24 bits
R
G
B
YUV
RGB
Y
Y-1
Y-2
UV
UV
U
U
Y
V
V
High-speed
conversion
Field-to-field
interpolation
interpolation
Vertical
expansion
filter
Horizontal
expansion
filter
Edge
enhancement
vertical
expansion
filter
DEMUX
Horizontal
expansion
filter
Horizontal
expansion
filter
Figure 2-8.
Figure 2-9.
2-3-2. Signal processing block diagram in SVP/YUV mode
XG-NV1U
18
2-3-3. Signal processing block diagram in SVP/YUV mode
R
G
B
R
G
B
Vertical
expansion
filter
Horizontal
expansion
filter
The vertical expansion filter provides for:
1
→
1 expansion (through)
4
→
5 expansion
2
→
3 expansion.
The horizontal expansion filter provides
for:
1
→
1 expansion (through)
4
→
5 expansion
9
→
10 expansion
An external input is given to select any of
the expansions.
Dummy
bit
Dummy
bit
One cycle
Repeated hereafter
The frequency is converted by the STG via the memory. As shown above, one dot
dummy bit is inserted for every 4 dots.
When displayed as it is, the image looks like that by the electronic zoom of the
XV670/690.
dummy bit is inserted for every 4 dots.
When displayed as it is, the image looks like that by the electronic zoom of the
XV670/690.
2-4. Concept of electronic zoom signal processing
(example: 4
→
5 conversion)
2-4-1. Concept of horizontal time base expansion by STG
Figure 2-10.
Figure 2-11.
XG-NV1U
19
2-4-2. Concept of SVP (digital smoothing filter)
0/4
4/4
1/4
3/4
2/4
2/4
3/4
1/4
4/4
0/4
The (x)-marked elements are multipliers, whereas the (+)-marked ones are adders.
The numbers in the near the multipliers show the multiplying coefficients (constants).
The numbers in the near the multipliers show the multiplying coefficients (constants).
Dummy bit
Input signal mode
Horizontal conversion factor
Vertical conversion factor
832 x 624
1
→
1
1
→
1
800 x 600
1
→
1
1
→
1
640 x 480 (without zoom)
1
→
1
1
→
1
640 x 480 (zoom)
4
→
5
4
→
5
640 x 400 (without zoom)
1
→
1
1
→
1
640 x 400 (zoom 1)
4
→
5
4
→
5
640 x 400 (zoom 2)
4
→
5
2
→
3
640 x 400 (without zoom)
1
→
1
1
→
1
720 x 400 (zoom 1)
9
→
10
4
→
5
720 x 400 (zoom 2)
9
→
10
2
→
3
NTSC
3
→
4
3
→
8
PAL/SECAM
9
→
10
9
→
20
2-4-3. Modes and conversion factors
Figure 2-12.
XG-NV1U
20
2-5. DGA IC Block Diagram
Figure 2-13.
SG
Test Pat.
BM Pat.
SG MUX
OSD MUX
8bit-6bit FRC
8bit-6bit FRC
8bit-6bit FRC
OSD MUX
OSD MUX
SG MUX
G-Gamma
RAM (LUT)
R-Gamma
RAM (LUT)
6 CH DIV
RGB MUX
REF data MUX
B-Gamma
RAM (LUT)
µ
COM I/F
S-BUS Control
Resister File
LCD Control
BM Control
REF Control
Timing gen.
SVP Control
RAM
Line data gen.
SG MUX
DGi[7..0]
DRi[7..0]
DBi[7..0]
HSTNi,VSTNi
UCSNi,UDTi,UCKi
ODDi
OSDCLKi (System clock)
XIN (20Mhz OSD PLL Control Onfy)
OSDGi,Ri,Bi,Ii,BKi (OSD)
F86MDi (ON/OFF Control)
CHMDi[1..0], DINVi (Div Mode, data invert Control)
CH1o[7..0]
CH2o[7..0]
CH3o[7..0]
CH4o[7..0]
CH5o[7..0]
CH6o[7..0]
DACKo[2..0] (D/A clk G,R,B)
HST2o[2..0], HCK1o[2..0],
HCK2o[2..0] (LCD Hstart, Hclk G,R,B)
VST1o,VST2o,VCKo,ENBo,PCGo
(LCD Control Sig.)
FRP1o,FRP2o,VBLKNo,REFWo,REFBK
MUXo[2..0] (REF Control Sig.)
IGFLGBo,
IDTo,ICKo
OSDHNo,OSDVNo (OSD PLL Control)
ALL Block
RAM buffer
OSD PLL Control
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