Sharp XG-NV1E (serv.man18) Service Manual ▷ View online
XG-NV1U
13
2. SIGNAL PROCESSING CIRCUIT
2-1. Block Diagram
TN
R
G
B
H
V
LM1204V
3-ch
video amplifier
ADC
AD9057BR
ADC
AD9057BR
ADC
AD9057BR
VS
Y
UV
H
V
SAA7110
IC1201
IX2985CE
STG
SDR AM 4M bit x 4
IX2895CE
MB81141625
IC1206
IX2960CE
SVP2
IC1001
IX2959CE
AGA
R
G
B
D
O
R
D
I
R
Y/R
Y
-1
/G
Y
+1
/B
UV
»
RGB/video input switching
In RGB mode
»
Time base expansion process
(horizontal/vertical)
»
Input frequency measurement
(horizontal/vertical)
»
Composit c input sync
separation
»
PLL control (clock frequency
division)
»
Phase adjuster circuit
In video mode
»
Time base expansion process
(horizontal/vertical)
»
Scan conversion
In RGB mode
»
Horizontal smoothing filter
»
Vertical smoothing filter
In video mode
»
YUV
→
RGB matrix
»
Horizontal smoothing filter
»
Vertical smoothing filter
»
Contour correction
»
Frame-to-frame
interpolation
»
6-phase channel
division
»
LCD panel control
signal
»
Gamma correction
»
OSD signal insertion
»
Black/blue
background
»
Video masking
»
Filter coefficient
generation
Figure 2-1.
XG-NV1U
14
2-2. STG (Signal Timing Generator)
R, CK•R, WE•R, RAS•R, CAS•R, CKE•R, A9~0
R, D15~0
SDRAM I/F
YA7~0
YB7~0
YC7~0
YD7~0
HSKLN
OHSY
ODD
CLK40M
OSDH
UDO
UCK
UDT
UCSNHTG
TG2
TG1
HSYNO
PDEN
HSYNE
ADCLK
DIVIDER
DOTCLK
C
V
H
Sync signal MUX
Clock MUX
Video input
SDRAM
matrix
ADCKIN
LLC
BIN7~0
GIN7~0
RIN7~0
SDRAM
video output
matrix
Sync signal polarity ID
Composite sync
signal separation
Sync signal MUX
Phase adjuster circuit
Frequency
measurement/
polarity ID
Microprocessor
interface
Figure 2-2.
XG-NV1U
15
2-2-1. Frequency measurement circuit
MUX
MUX
CLK
CLK
CLR
CLR
TRIG
TRIG
RL
RD
MUX
Line counter
Counter
Latch
Counter
Latch
Dot counter
To microprocessor bus
CLK40M (reference clock)
V sync signal
V sync signal of
composite
sync signal
composite
sync signal
H sync signal
H sync signal
of composite
sync signal
of composite
sync signal
1nS Delay (Typ.)
128 to 1 MUX
×
127
HSYNO
HSYNO
ADCLK
Input signal's
horizontal period
horizontal period
Select signal
Input signal's
horizontal period
horizontal period
Video signal
Delay by
adjuster circuit
adjuster circuit
On the NV1, the CLK40M reference clock is of 43.98 MHz.
The horizontal frequency HF (kHz) andvertical frequency VF (Hz) are determined as follows.
HF = 43.98 x 1000
The horizontal frequency HF (kHz) andvertical frequency VF (Hz) are determined as follows.
HF = 43.98 x 1000
÷
RD,
VF = HF x 1000
÷
RL
The frequencies obtained thus are employed in identifying the RGB mode.
2-2-2. PHASE adjuster circuit
In order to vary the phase, the horizontal sync delay is provided by the buffer as shown below.
Figure 2-3.
Figure 2-4.
XG-NV1U
16
2-2-3. Out-of-PHASE signals
Signal 1
Signal 2
Signal 3
Setup time
Hold time
Red
Green
Blue
Red
Green
Blue
RAMB
[7. . 0]
[7. . 0]
RAMA
[15. . 8]
[15. . 8]
RAMB
[15. . 8]
[15. . 8]
RAMD
[7. . 0]
[7. . 0]
RAMC
[15. . 8]
[15. . 8]
RAMD
[15. . 8]
[15. . 8]
Top half
Bottom half
RAMA
[15..8]=Y
[7..0]=UV
[7..0]=UV
RAMB
RAMC
RAMD
Time base
Repeated hereafter
Field +3
Field +2
Field +1
Field +0
Figure 2-5.
Figure 2-7.
Figure 2-6.
a) Video signal versus memory (SDRAM) data in RGB mode
b) Video signal versus memory (SDRAM) data in YUV (video) mode
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