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SYMBOL

PIN

RESET

32

CGCE

33

V

DD

34

V

SS

35

HCL

36

HSY

37

HS

38

PLIN(HL)

39

ODD(VL)

40

VS

41

HREF

V

SS

43

V

DD

44

DESCRIPTION

Reset active LOW input/output (CGCE=1, output; CGCE=0, input); sets the device into a

defined state. All data outputs are in high impedance state. The I

2

C-bus is resel (waiting

for START condition). Using the external CGC, the LOW period must be maintained for at

least 30 LLD clock cycles.

CGC Enable active HIGH input (CGCE=1, on-chip CGC active; CGCE=0, external CGC

mode, use SAA7197).

supply voltage (+5V)

ground

Horizontal Clamping input/output pulse (programmable via I

2

C-bus bit PULIO: PULIO=1,

output; PULIO=0, input). This signal is used to indicate the black level clamping period for

the analog input interface. The beginning and end of its HIGH period (only in the output

mode) can be programmed via the I

2

C-bus registers 03H, 04H in 50 Hz mode and regis-

ters 16H, 17H in 60Hz mode, active HIGH.

Horizontal Synchronization input/output indicator (programmable via I

2

C-bus bit PULIO:

PULIO=1, output; PULIO=0, input). This signal is fed to the analog interface. The beginning

and end of its HIGH period (only in the output mode) can be programmed via the I

2

C-bus

registers 01H, 02H in 50Hz mode and registers 14H, 15H in 60Hz mode ,active HIGH.

Horizontal Synchronization output (programmable; the HIGH period is 128 LLC clock cycles).

The position of the positive slope is programmable in 8 LLC increments over a complete line

(64µs) via the I

2

C-bus register 05H in 50 Hz mode or register 18H in 60 Hz mode.

PAL Identifier Not output; marks for demodulated PAL signals the inverted line

(PLIN=LOW) and a non-inverted line (PLIN=HIGH) and for demodulated SECAM the DR

line (PLIN-LOW) and the DB line (PLIN=HIGH). Select PLIN function via I

2

S-bus bit

RTSE=0. (H-PLL locked output; a HIGH state indicates that the internal PLL has locked.

Select HL function via I

2

C-bus bit RTSE=1).

ODD/EVEN field identification output; a HIGH state indicates the odd field. Select ODD

function via I

2

C-bus bit RTSE=0.

(Vertical Locked output; a HIGH state indicates that the internal Vertical Noise Limiter

(VNL) is in a locked state. Select VL fundtion via I

2

C-bus bit RTSE=1).

Vertical Synchronization input/output (programmable via I

2

C-bus bit OEHV: OEHV=1,

output; OEHV=0, input). This signal indicates the vertical synchronization with respect to

the YUV output. The high period of this signal is approximately six lines if the VNL func-

tion is active. The positive slope contains the phase information for a deflection controller,

for example the TDA9150. In input mode this signal is used to synchronize the vertical

gain and clamp blanking stage, active HIGH.

Horizontal Reference output; this signal is used to indicate data on the digital YUV-bus.

The positive slope marks the beginning of a new active line. The HIGH period of HREF is

either 768 Y samples or 640 Y samples long depending on the detected field frequency

(50/60 Hz mode). HREF is used to synchronize data multiplexer/demultiplexers. HREF is

also present during the vertical blanking interval.

ground

supply voltage (+5V)

SYMBOL

PIN

Y7

45

Y6

46

Y5

47

Y4

48

Y3

49

Y2

50

V

SS

51

V

DD

52

Y1

53

Y0

54

UV7

55

UV6

56

UV5

57

UV4

58

UV3

59

UV2

60

UV1

61

UV0

62

FEIN

63

(MUXC)

GPSW

64

(VBLK)

XTALO

65

XTALI

66

V

SS

67

V

DD

68

DESCRIPTION

Upper 6 bits of the 8-bit luminance (Y) digital output. As part of the digital YUV-bus (data

rate LLC/2), or A/D2(3) output (data rate LLC/2) selectable via I

2

C-bus bit SQPB=1.

ground

supply voltage (+5V)

Lower 2 bits of the 8-bit luminance (Y) digital output. As part of the digital YUV-bus (data

rate LLC/2), or A/D2(3) output (data rate LLC/2) selectable via I

2

S-bus bit SQPB=1.

8-bit digital UV (colour difference) output; multiplexed colour difference signal for U and V

component of demodulated CVBS or chrominance signal. The formet and multiplexing

scheme can be selected via I

2

C-bus control. These signals are part of the digital YUV-bus

(data rate LLC/2), or A/D3(2) output (data rate LLC/2) selectable via I

2

C-bus bit SQPB=1.

Fast Enable input (active LOW); this signal is used to control fast switching on the digital

YUV-bus. A high at this input forces the IC to set its Y and UV outputs to the high imped-

ance state. To use this function set I

2

C-bus bits MS24 and MUYC to LOW.

(Multiplex Components input; control signal for the analog multiplexers for fast switching

between locked Y/C signals or locked CVBS signals. FEIN automatically fixed to LOW

(digital YUV-bus enabled), if one of the three MUXC functions are selected (MS24 or

MS34 or MUYC=HIGH).

General Purpose Switch output; the state of this signal is programmable via I

2

C-bus

register oDh, bit 1. Select GPSW function via I

2

C-bus bit VBLKA=0. (Vertical Blank test

output; select VBLK via I

2

C-bus bit VBLKA=1).

Crystal oscillator output (to 26.8 MHz crystal); not used if TTL clock is used.

Crystal oscillator input (from 26.8 MHz crystal) or connection of external oscillator with

TTL compatible square wave clock signal.

ground

supply voltage (+5V)

VSSA4

10

AI42

11

VDDA4

SAA7110

SAA7110A

12

AI41

13

VSSA3

14

AI32

15

VDDA3

16

AI31

17

VSSA2

18

AI22

19

VDDA2

20

AI21

21

VSS(S)

22

AOUT

23

VDDA0

24

VSSA0

25

LFCO

26

VDD

27

VSS

28

LLC

29

LLC2

30

CREF

31

RESET

32

CGCE

33

VDD

34

VSS

35

HCL

36

HSY

37

HS

38

PLIN (HL)

39

ODD (VL)

40

VS

41

HREF

42

VSS

43

UV2

60

UV3

59

UV4

58

UV5

57

UV6

56

UV7

55

Y0

54

Y1

53

VDD

52

VSS

51

Y2

50

Y3

49

Y4

48

Y5

47

Y6

46

Y7

45

VDD

44

i.c.

9

i.c.

8

i.c.

7

SCL

6

SDA

5

SA

4

RTCO

3

AP

2

SP

1

VDD

68

VSS

67

XTAL1

66

XTAL0

65

GPSW (VBLK)

64

FEIN (MUXC)

63

UV0

62

UV1

61

The SAA7110;SAA7110A offers six analog signal inputs, two analog main channels with clamping circuit, analog
amplifier, anti-alias filter and CMOS ADC. A third analog channel also with clamping circuit, analog amplifier and
anti-alias filter can be added or switched to both main channels directly before the ADCs.

The clamping control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. The normal digital clamping level for luminance or CVBS signals is 64
and for chrominance signals is 128. The anti-alias filters are adapted to the clock frequency. The vertical blanking
control circuit generates an I

2

C-bus programmable vertical blanking pulse. During the vertical blacking time gain

and clampingcontrol are frozen.

The fast switch control circuit is used for special applications.

The coupling capacitor is used is clamp capacitance for each input. An internal digital clamp comparator generates
the information concerning clamp-up or clamp-down. The clamping levels for the two ADC channels are adjustable
over the 8-bit range (1 to 254). Clamping time in normal use is set with the HCL pulse at the back porch of the video
signal. The clamping pulse HCL is user adjustable.

The 8-bit chrominance signal passes the input interface, the chrominance bandpass filter to eliminate DC components,
and is finally fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the
local oscillator DTO1 with 90 degrees phase shift are applied. The frequency is dependent on the present colour
standard.

The multiplier operates as a quadrature demodulator for all PAL and NTSC signals; it operates as a frequency
down mixer for SECAM signals.
The two multiplier output signals are converted to a serial UV data stream and applied to two low-pass filter stages,
then to a gain controlled amplifier. A final multiplexed low-pass filter achieves, together with the preceding stages,
the required bandwidth performance.

The PAL and NTSC originated signals are applied to a comb filter.

The signal originated from SECAM is fed through a Cloche filter (o Hz centre frequency), a phase demodulator and
a differentiator to obtain frequency demodulated colour difference signals. The SECAM signal is fed after de-
emphasis to a cross-over switch, to provide both the serial transmitted colour difference signals. These signals are
fed to the BCS control and finally to the output fomatter stage and to the output interface.

The 8-bit luminance signal, a digital CVBS format or a luminance format (S-VHS, Hi8), is fed through a switchable
prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter
(fc=4.43 or 3.58 MHz centre frequency selectable) eliminates most of the colour carrier signal, therfore, it must be
bypassed for S-Video (S-VHS, Hi8) signals.

The high frequency components of the luminance signal can be peaked (control for sharpness improvement via
I

2

C-bus) in two bandpass filters with selectable transfer characteristics.

A coring circuit with selectable characteristics improves the signal once more. The signal is then added to the
original (unpeaked) signal. A switchable amplifier achieves common DC amplification, because the DC gains are
different in both chrominance trap modes.

The improved luminance signal is fed via the variable delay to the BCS control and the output interface.