Sharp XG-NV1E (serv.man18) Service Manual ▷ View online
XG-NV1U
69
CONTROL BITS
8-8-14. Subaddress 2D (DATA BYTE 111 to 104)
Integration value gain (IVAL)
8-8-15. Subaddress 2E (DATA BYTE 119 to 112)
Blanking pulse VBLK-set (VBPS)
DECIMAL
SET LINE NUMBER
MULTIPLIER
(step size = 2)
CONTROL BITS
IVAL7
IVAL6
IVAL5
IVAL4
IVAL3
IVAL2
IVAL1
IVAL0
1
0
0
0
0
0
0
0
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
255
1
1
1
1
1
1
1
1
VBPS7 VBPS6 VBPS5 VBPS4 VBPS3 VBPS2 VBPS1 VBPS0
0
0 after rising edge of VS
0
0
0
0
0
0
0
0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
131
(1)
262 after rising edge of VS
1
0
0
0
0
0
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
156
(2)
312 after rising edge of VS
1
0
0
1
1
1
0
0
8-8-16. Subaddress 2F (DATA BYTE 127 to 120)
Blanking pulse VBLK-reset (VBPR)
DECIMAL
SET LINE NUMBER
MULTIPLIER
(step size = 2)
CONTROL BITS
VBPR7 VBPR6 VBPR5 VBPR4 VBPR3 VBPR2 VBPR1 VBPR0
0
0 after rising edge of VS
0
0
0
0
0
0
0
0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
131
(1)
262 after rising edge of VS
1
0
0
0
0
0
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
156
(2)
312 after rising edge of VS
1
0
0
1
1
1
0
0
Notes:
1. Maximum for 60 Hz.
2. Maximum for 50 Hz.
2. Maximum for 50 Hz.
Notes:
1. Maximum for 60 Hz.
2. Maximum for 50 Hz.
2. Maximum for 50 Hz.
DECIMAL INTEGRATION VALUE GAIN
XG-NV1U
70
8-8-17. Subaddress 30 (DATA BYTE 135 to 128)
ADCs gain control
FUNCTION
CONTROL BITS
Fix gain ADC cahnnel 2 (GAD2) ; data bits D1 and D0
0 dB
GAD21 = 0 ; GAD20 = 0
0.05 dB
GAD21 = 0 ; GAD20 = 0
0.10 dB
GAD21 = 1 ; GAD20 = 0
0.15 dB
GAD21 = 1 ; GAD20 = 1
Gain ADC select channel 2 (GAS2) ; data bit D2
Fix gain vial I
2
C-bus GAD2
GAS2 = 0
Automatic gain via loop
GAS2 = 1
Fix gain ADC channel 3 (GAD3) ; data bits D4 and D3
0 dB
GAD31 = 0 ; GAD30 = 0
0.05 dB
GAD31 = 0 ; GAD30 = 1
0.10 dB
GAD31 = 1 ; GAD30 = 0
0.15 dB
GAD31 = 1 ; GAD30 = 1
Gain ADC select channel 3 (GAS3) ; data bit D5
Fix gain vial I
2
C-bus GAD3
GAS3 = 0
Automatic gain via loop
GAS3 = 1
White peak mode select (WISL) ; data bit D6
Difference value integration
WISL = 0
Fix value integration
WISL = 1
XG-NV1U
71
8-8-18. Subaddress 31 (DATA BYTE 143 to 136)
Mixer control #3
FUNCTION
CONTROL BITS
Pulses I/O control (PULIO) ; data bits D0
HCL and HSY to input pins
PULIO = 0
HCL and HSY to output pins
PULIO = 1
Pin function switch (VBLKA) ; data bit D1
GPSW cative (normal)
VBLKA = 0
VBLK test output active
VBLKA = 1
DMSD-SQP bypassed (SQPB) ; data bit D3
DMSD data to YUV output
SQPB = 0
A/D data to YUV output
for test purposes only (do not use)
White peak slow up integration enable (WRSE) ; data bit D4
Hold in white peak mode
WRSE = 0
Slow up integration with 1 value in H or V
(dependent on WIRS)
White peak slow up integration select (WIRS) ; data bit D5
Slow up integration with 1 value per line
WRIS = 0
Slow up integration with 1 value per field
WRIS = 1
Analog test select (AOSL) ; data bits D7 and D6
AOUT connected to ground
AOSL1= 0 ; AOSL0 = 0
AOUT connected to input AD2
AOSL1= 0 ; AOSL0 = 0
AOUT connected to input AD3
AOSL1= 1 ; AOSL0 = 1
AOUT connected to channel 4
AOSL1= 1 ; AOSL0 = 1
SQPB = 1
WRSE = 1
CONTROL BITS
8-8-19. Subaddress 32 (DATA BYTE 151 to 144)
Integration value white peak (WVAL)
WVAL7 WVAL6 WVAL5 WVAL4 WVAL3 WVAL2 WVAL1 WVAL0
1
0
0
0
0
0
0
0
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
127 (max.)
0
1
1
1
1
1
1
1
DECIMAL INTEGRATION VALUE
WHITE PEAK
XG-NV1U
72
8-8-21. Subaddress 34 (DATA BYTE 167 to 160)
Gain updata level (GUDL ; data bits D5 to D0)
8-8-20. Subaddress 33 (DATA BYTE 159 to 152)
Mixer control #4
FUNCTION
CONTROL BITS
Clock select AD2 (CAD2) ; data bit D2
LLC for test purposes only (do not use)
CAD2 = 0
LLC/2
CAD2 = 1
Clock select AD3 (CAD3) ; data bit D3
LLC for test purposes only (do not use)
CAD3 = 0
LLC/2
CAD3 = 1
Change sign bit UV data (CHSB) ; data bit D5
UV output unipolar
CHSB = 0
UV output two's complement
CHSB = 1
Output format select (OFTS) ; data bit D7
4 : 1 : 1 format
OFTS = 0
4 : 2 : 2 format
OFTS = 1
GUDL5 GUDL4 GUDL3 GUDL2 GUDL1 GUDL0
0
0 LSB
> 0
0
0
0
0
0
0
↓
↓
↓
↓
↓
↓
↓
↓
↓
7
±7 LSB
> 7
0
0
0
1
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
> 31
off
always
1
X
X
X
X
X
FUNCTION
CONTROL BITS
No phase delay
MUD2 = 0 ; MUD1 = 0
1 LLC cycle phase delay for CLAA path
MUD2 = 0 ; MUD1 = 1
2 LLC cycle phase delay for CLAA path
MUD2 = 1 ; MUD1 = 0
3 LLC cycle phase delay for CLAA path
MUD2 = 1 ; MUD1 = 1
MUXC phase delay (MUD2) ; data bits D7 and D6
CONTROL BITS
DECIMAL
HYSTERESIS
FOR 8-IT GAIN
UPDATE
NEW GAIN-OLD GAIN
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