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UP-X500U

DIagnostics Specifications

4 – 26

The read test of the contactless clerk key is performed.

•  UP-X500 system unit diagnostic test execution media   x 1

The following items will be checked:
Contactless clerk key
Error table 

The read data of the contactless clerk key is displayed.

A list of error information on (1) Contactles Clerk Key Test recorded in
DRAM is displayed.

If no error occurs, OK or NO ERROR is displayed.

With the above screen displayed, select the test item you want to exe-
cute using [

2

] and [

4

] keys, and then press [ENTER] to execute the test.

You can return to the initial menu screen by pressing the [ESC] key.

The number of the clerk key connected to the system unit is displayed.

The display returns to the initial screen when any key is pressed.

Erroneous read data end code

No send data cannot be written.

The PCP3 firmware is updated.

•  UP-X500 system unit diagnostic test execution media   x 1

The following items are checked by this test:

PCP3 Update

Error table

The PCP3 firmware is updated.

A list of error information on (1) PCP3 Update recorded in DRAM is displayed.

If no error occurs, OK or NO ERROR is displayed.

With the above screen displayed, select the test item you want to exe-
cute using the [

2

] and [

4

] keys, and then press the [ENTER] key to

execute the test.

You can return to the initial menu screen by pressing the [ESC] key.

With the above screen displayed, type "184184" using the numeric keypad.

EEPROM will be initialized and then the execution screen will appear.

You can return to the menu screen by pressing the [ESC] key.

The PCP3 firmware unloader is executed and the result is displayed.
The display will return to the initial menu screen when any key is pressed.

㪚㫆㫅㫋㪸㪺㫋㫃㪼㫊㫊㩷㪚䌬䌥䌲䌫

 

䌋䌥䌹

 

䌔䌥䌳䌴

 

㪚㫆㫅㫋㪸㪺㫋㫃㪼㫊㫊㩷

C

䌬䌥䌲䌫

 

䌔䌥䌳䌴

 

Error Table

CURSOR: Move             NTER: Select             ESC: Exit

Contactless Clerk Key Code Display

Clerk Key Code : XX XX XX XX XX XX XX XX

Press any Key to Exit. 

PCP3 UPDATE

PCP3 UPDATE
Error Table

CURSOR: Move          ENTER: Select                ESC: Exit

ESC: Exit

Operation press  "184184" to execute.

PCP3 UPDATE

OK

Press any Key to Exit.

UP-X500V

CIRCUIT DESCRIPTION

5 – 1

Item

UP-X500

CPU

CPU

VIA Eden: 800MHz 

BUS clock

133MHz

L1, L2 Cashe

CPU Built-in (128kB, 64kB)

CPU fun

NO

Chipset/Companion

CLE266

Memory

Standard Spec

DDR-SDRAM PC2100

Size

128MB

184pinDIMM

Option

Spec

DDR-SDRAM PC2100
184 pinDIMM (Max.512MB)

Socket 1

E C C
support

No

BIOS/BOOT

4M bit Flash PROM

PCI

No

3.5'FDD

No

IDE port

Spec

UltraATA100

Primary

Master

Secondary

No

DISK

Standard

HDD 30GB

Option

No

Display (LCD)

Size

12.1inch TFT color

Resolution

XGA

Display controller

Controller

CLE26 Built-in

CPU I/F

AGP x 4 (LSI Internal connection)

VRAM

8~64MB (Soft setup)

RGB output

No

Touch Panel

Touch panel

Fujitsu4wire 

Controller

FUjitsu

CPU I/F

USB

Ethernet

100 Base-TX/10Base-T

Sound

Controller

No

Mono-speaker

Yes (BEEP only)

Stereo lineout

No

Sirial port

16550 Fast UART Compatible

Controller

NS SIO10N268

External Channel

3

COM1

D.Sub9pin

COM2

D.Sub9pin (Ci signal/+5V soft-
warecontrol)

COM3

D.Sub9pin

CustomerDisplay

COM4

Controller

NS SIO10N268 

UP-P20DP

RJ45

UP-I20DP

  (UP-I20DP only)

External
Parallelport

Spec

LPT1

Controller

NS SIO10N268

Channel

1

Connecter

D.sub25pin

USB port

USB2.0 x 2

PS/2

Yes

PC-CARD I/F

Spec

Card-bus,16bitPCMCIA-Card

Controller

RICHO R5C486

Slot

2

Magnetic card
reader

Spec

3 trackreader

Controller

PCP

III

Option

No

DrawerI/F

Controller

PCP

III

Connecter

2

POS key board

No

POS Printer

No

LED

HDD access

No

LAN access

No

Power

Yes

SWITCH

AC Power switch

WMF clark I/F

Standard

Yes (V only)

Controller

PCP

III

Contactless
clark I/F

Standard

Yes (V only)

Controller

UART

Battery

C.MOS RAM BackupLithium

Item

UP-X500

UP-X500V

CIRCUIT DESCRIPTION

5 – 2

CPU

ESP8000

(ESP7000) 

North

VT8623

(CLE266) 

DIMM

㬍

2

DDR-SDRAM

128MB 

TOUCH

Clock Gen.  

RGB. 

LCD

VLINK 4X 

Thermal

Sensor 

South
VT8235 

CPU P.S. 

PHY

LVT6103 

LAN 

LCD cont. 

SMbus 

INV. 

LVDS 

CARD-Bus

R5C486 

 

 

PCI 

PCCARD 

 TPC 

 

USB 

Ultra-I/O
SIO10N268 

 PS2 

LPC 

   

HDD 

IDE 

IDE 

MCR

COM3

COM2

COM1

   

POS MCU

PCP3 

WMF
DRAWER

 2

   XBUS

Rear-DP

D/R

D/R

D/R

D/R

LPT1 

DC-DC

POWER

SUPPLY

BIOS ROM 

   

UART

(Vonly)

C16550 

CLERK 

POWER SUPPLY UNIT 

䋨

AC ADAPTOR

䋩

USB

㬍

2

Dr.

UP-X500V

CIRCUIT DESCRIPTION

5 – 3

Peripheral Controller for POS (

III

) (hereafter called PCP

III

) uses Hita-

chi microprocessor H8S2138 and has the following functions:

•  Magnetic card read and write control

• Clock control

•  Clerk key I/F

• Drawer I/F

•  General-purpose input port (x8 bit) and input/output port (x 8 bit) control

The PCP

III

 sends and receives commands and data to and from the

host CPU through two host interfaces which are classified by function
into the following two categories:

The PCP

III

 executes commands from the host CPU on a multitask operation

basis. There is a possibility that data are not returned to the CPU in the order
the PCP

III

 has received. The order of data should be identified by the identifi-

cation code contained in data to be returned from the PCP

III

 to the host CPU.

The addresses to which a command and data from the host CPU to the
PCP

III

 are different. Therefore, the PCP

III

 analyzes a command it has

received and waits for necessary data. It is thus necessary to send a com-
mand and data from the host CPU to the PCP

III

 as a matched pair. 

It is not until the PCP

III

 analyzes a command and receives necessary data

that it executes the instruction.
If the number of data following a command is not as specified, the results is as
follows.

• The PCP

III

 waits for data for good.

• The PCP

III

 ignores the instruction and the data whose number is

insufficient when it receives a new instruction before receiving the
necessary number of data.

The number of data required by a command is taken and the subsequent
data are ignored.

3

Commands and data for devices sent from the host CPU to the PCP

III

are once stored in the host receive buffer. Commands and data stored
are then sent to the input buffer of each device. 
If any one of the input buffers becomes full, the subsequent commands
and data sent from the host CPU to the PCP

III

 are stored in the host

receive buffer. If the host receive buffer is full, it no longer receives com-
mands and data from the host CPU.

3

Data and status sent from each device to the host CPU are once stored in
the host send buffer and then sent to the host according to the read action
of the host CPU.
If data and status sent from each device to the host CPU cannot be stored
because the host CPU does not read the content of the host send buffer,
the processing of a command given from the host CPU is suspended in
principle. For this reason, if sending of commands and data from the host
CPU to the PCP

III

 is continued, the host receive buffer becomes full, mak-

ing it impossible to receive commands and data any further.

Three tracks of data can be read simultaneously and 1 track of data can be
written.
The room key card of magnetic stripe record type (Miwa Lock) is the JIS-

II

type (JBA), but the start code of the JIS-type's second track (ABA) or the JIS-

I

type's first track (JATA) is recorded at the beginning of the magnetic stripe.
As a result, when the start code is automatically identified by the controller,
data of the JIS 

II

 type cannot be read. Therefore, a special measure for the

JIS 

II

 type has been taken instead of performing automatic identification of the

start code.
To avoid this problem, the magnetic card will be decoded by the host CPU.
Therefore, bit data received by the PCP

III

 will be sent to the host CPU as it is.

In addition, written data will also be sent from the host CPU to the PCP

III

 as

bit data. This makes it possible to support any type of magnetic stripe record-
ing. It will also be possible to analyze read errors of a demagnetized magnetic
card.

Function

Interface

Host interrupt signal

Magnetic card 

Host interface ch1

HiRQ12

Other than above

Host interface ch2

HiRQ11

Host CPU

PCP

III

Instruction for device 1

3

Instruction for device 2

3

1

Data returned to device 2

1

Data returned to device 1

PCP

III

䉟

RST

VCC

/RES

8

Drawer

Drawer

Power supply

Host CPU

H

o

st

 in

te

rf

a

c

e

H

o

st

 in

te

rf

a

c

e

Charge/discharge

control IC [BC]

Clerk key

S

y

nc

hr

o

n

o

u

s s

e

ri

a

l

S

y

nc

hr

o

n

o

u

s s

e

ri

a

l

S

y

nc

hr

o

n

o

u

s s

e

ri

a

l

Magnetic card device

Clock

General-purpose

I/O port

Host interface

Host

send

buffer

Host

receive

buffer

Device 1

Device 2

Device 3

Device 4