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Model
UP-X500 (serv.man4)
Pages
75
Size
1.38 MB
Type
PDF
Document
Service Manual
Brand
Device
EPOS / UP-X500 Service Manual
File
up-x500-sm4.pdf
Date

Sharp UP-X500 (serv.man4) Service Manual ▷ View online

UP-X500V
CIRCUIT DESCRIPTION
5 – 4
PIN TABLE
Here is the pin table for the PCP
III
I
HOST INTERFACE
Bus control
No.
Function
Remarks
I/O
1
/RES
Input
2
XTAL
3
EXTAL
4
MD1
Input
5
MD0
Input
6
NMI
Input
7
/STBY
Input
8
VCC2
9
MCR_RCP1
SCK0
Input
10
MCR_RDD1#
RxD0
Input
11
MCR_DiN1#
TxD0
Output
12
VSS
13
B-D1
P97
I/O
14
B-D0
P96
I/O
15
/CS1
Input
16
/IOW
Input
17
/IOR
Input
18
 MCR_CSL1#
IRQ0#
Input
19
 MCR_CLS2#
IRQ1#
Input
20
 MCR_CLS3#
IRQ2#
Input
21
Pio0
P60
22
Drawer1 IN
P61
Input
23
Drawer1 OUT
FTOA
Output
24
MCR_RWC1#
P63
Output
25
MCR_WTS1
P64
Input
26
Drawer2 IN
P65
Input
27
Drawer2 OUT
FTOB
Output
28
/B-SEL
P67
Output
29
AVCC
30
MCR_0
P70
Input
31
MCR_1
P71
Input
32
Pi2
P72
Input
33
Pi3
P73
Input
34
Pi4
P74
Input
35
Pi5
P75
Input
36
Pi6
P76
Input
37
/B-ACK
P77
Input
38
AVSS
39
LED_PWR#
P40
Output
40
 MCR_RDD3#
RxD2
Input
41
MCR_RCP3
SCK2
Input
42
HIRQ11
Output
43
Pio1
P44
I/O
44
HIRQ12
Output
45
Pio2
P46
I/O
46
Pio3
P47
I/O
47
VCC1
48
Clerk DATA7
P27
Input
49
Clerk DATA6
P26
Input
50
Clerk DATA5
P25
Input
51
Clerk DATA4
P24
Input
52
Clerk DATA3
P23
Input
53
Clerk DATA2
P22
Input
54
Clerk DATA1
P21
Input
55
Clerk DATA0
P20
Input
56
VSS
57
Alarm_CLK
P17
Output
58
Alarm_DATA
P16
I/O
59
Alarm_CE
P15
Output
60
Pio4
P14
I/O
61
Pio5
P13
I/O
62
Pio6
P12
I/O
63
Pio7
P11
I/O
64
/B-STB
P10
Output
65
HDB0
I/O
66
HDB1
I/O
67
HDB2
I/O
68
HDB3
I/O
69
HDB4
I/O
70
HDB5
I/O
71
HDB6
I/O
72
HDB7
I/O
73
VSS
74
HA0
Input
75
/CS2
Input
76
Pi0
P82
Input
77
Pi1
P83
Input
78
Drawer-IN
IRQ3#
Input
79
MCR_RDD2#
RxD1
Input
80
MCR_RCP2
SCK1
Input
Host CPU side
Direction of
data flow
Type
PCP
III
 side
/CS1 /CS2 HA0 /WR
/RD
Host CPU
PCP 
III
Name
Abb
R/W
0
1
0
0
1
3
Data
Input
register1
IDR1
R
0
1
1
0
1
3
Command
0
1
0
1
0
1
Data
Output
register
ODR
W
R
0
1
1
1
0
3
Status
Status
register1
STR1
W
R
1
0
0
0
1
3
Data
Input
register2
IDR2R
R
1
0
1
0
1
3
Command
1
0
0
1
0
1
Data
Output
register2
SODR
2
W
R
1
0
1
1
0
1
Status
Status
register2
STR2
R
W
No.
Function
Remarks
I/O
UP-X500V
CIRCUIT DESCRIPTION
5 – 5
REGISTER
Input data registers 1/2 (ODR1/2)
This is an 8-bit read/write enable register for the PCP
III
 and 8-bit read-
only register for the host CPU.
The initial value is undefined when the system is reset or in the stand-by
mode.Register
Output data registers 1/2 (ODR1/2)
This is an 8-bit read/write enable register for the PCP
III
 and 8-bit read-
only register for the host CPU.
The initial value is undefined when the system is reset or in the stand-by
mode.
STATUS REGISTER 1/2 (STR1/2)
This shows the status of host interface processing.
Error (ERR)
This indicates that the main routine of the PCP
III
 is destroyed and the
loader of the boot block A or B waits for loading of write/erase control
program. 
Command/data (C/D)
When the host CPU writes data to IDR, the status of HA0 is written and
whether the content of IDR is data or command is identified.
Ready/Busy (R/B)
This register indicates that the PCP
III
 is performing internal processing
and cannot receive any command from the host.
The bit becomes 0 when:
• The PCP
III
 is initialized after turned on
• The PCP
III
 does not want to receive any command (data) from the
hostor any reason although the input data register full (IBF) is 0.
Input data register full (IBF)
When the host CPU writes data in the IDR, the IBF bit is set to 1. This
becomes a factor for internal interruption against the PCPIII.
When the PCP
III
 reads data from the IDR, the IBF bit is cleared to 0.
Data read from the IDR is once stored in the host receive buffer com-
posed of the ring buffer.
If the host receive buffer is full, IBF interruption should be inhibited and
any command from the host should not be received.
Output data register full (OBF)
When the PCP
III
 writes ODR, the OBF bit is set to 1.
When the host CPU read ODR, the OBF bit is cleared to 0.
4. HOW TO USE AS THE UP-X500.
4-1. I/O ADDRESSES
Bit
:
7
6
5
4
3
2
1
0
IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0
Initial value
:
---
---
---
---
---
---
---
---
PCP
III
:
R
R
R
R
R
R
R
R
Host  CPU
:
W
W
W
W
W
W
W
W
Bit
:
7
6
5
4
3
2
1
0
IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0
Initial value :
---
---
---
---
---
---
---
---
PCP
III
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Host  CPU
:
R
R
R
R
R
R
R
R
Bit
:
7
6
5
4
3
2
1
0
IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0
Initial value :
---
---
---
---
---
---
---
---
PCP
III
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Host  CPU
:
R
R
R
R
R
R
R
R
0 :  PCP
III
 operates normally
1 : Waits for loading of write/erase control program
0 : The content of input data register (IDR1/2) is data
1 : The content of input data register (IDR1.2) is a command.
0
:  PCP
III
 is busy and cannot receive commands from host.
1
:  PCP
III
 is ready for receiving commands from host.
0
: [Clear condition] PCP
III
 reads IDR.
1
: [Set condition] Host CPU writes IDR.
0 : [Clear condition] Host CPU read ODR.
1 : [Set condition] PCP
III
 writes ODR.
ch
I/O address
R/W
Type
Register
Interruption
Host interruption
Control device
1
7F0h
R
Data 
Output register 1 (ODR1)
HiRQ12
iRQ15
Magnetic card Command
W
Data 
Output register 1 (iDR1)
7F1h
R
Status
Status register 1 (STR1)
W
Status
Input register 1 (DR1)
2
7F2h
R
Data 
Output register 2 (ODR2)
HiRQ11
iRQ15
Other than others
W
Data 
Output register 2 (iDR2)
7F3h
R
Status
Status register 2 (STR2)
W
Command
Input register 2 (DR2)
UP-X500V
CIRCUIT DESCRIPTION
5 – 6
4-2. HOW TO USE GENERAL-PURPOSE PORTS
4-2-1.Input ports
The program identifies the model name according to the model identification
numbers 0 - 3.  By using this function, the following functions can be added.
•  Software that runs only on the said model.
•  Security that uses data encoded only by the said model.
4-2-2. I/O port
(1) 5V1
Controls the supply of +5V output to COM2.
(2) 5V2
Controls the supply of +5V output to the customer display.
4-3. CLOCK
RICHO real time clock RV5C339A. The alarm function is not used.
4-4. BC
The charge/discharge control function of the Nickel-hydrogen battery is
not used.
4-5. SERIAL I/F
With a special program, it is possible to write PCP
III
 firmware through the
COM1.
5. FUNCTIONAL SPECIFICATIONS
5-1. OUTLINE
This MCU is a touch panel controller which can be operated as the
standard HID under the USB host controller. It supports a 4-wire and 7-
wire resistance film touch panels.
It provides 3 buttons (left, right and center), scroll buttons (four direc-
tions), and 13-bit absolute coordinates for the USB host. Disconnect is
emulated by detecting the Low level/edge of the USB Disable signal.
After disconnecting by the Low level edge, Connect is emulated by
detecting the High level edge.
This MCU does not have a correction function. An application including
correction function is installed by installing a special device driver to the
said OS.
5-2. CONFIGURATION
The shaded part in the above sketch indicates the MCU.
For detail of the diagram, see the circuit diagram C1NC41120-0015.
Note that the specified function of the MCU is best obtained using our
genuine device driver.
5-3. PIN ARRANGEMENT AND FUNCTION
5-3-1.Pin arrangement diagram (7-wire type)
Pin Function
Pi0
Model identification 0
Pi1
Model identification 1
Pi2
Model identification 2
Pi3
Model identification 3
Pi4
Pi5
Pi6
Model identification
Model name
3
2
1
0
UP-X500
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Pin
Function
I/O
Pio0
5V1
Output
Pio1
Reserved (5V2)
Output
Pio2
Pio3
Pio4
Pio5
Pio6
Pio7
1 : Does not supply power 
0 : Supplies power
1 : Does not supply power
0 : Supplies power.
MCU 
M37534 
10bit ADC 
USB I/F 
Application
(Correction tool, user mode driver, control panel)
USB driver
(Windows98/ME/
 Win2K/WinXP)
Pen operation
Jumper wire
External
signal wire
4-wire panel
EP0
EP1









10 
11 
12 
13 
14 
15 
16 
17 
18 
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
< D+ 
< D- 
< Button Middle 
< Button Right 
< Button Left 
< PSW0 
< PSW2 
< PSW1 
< PSW4 
< PSW3 
< USB Vrefout 
< Module Disable 
< JPMODE 
< Wheel Down 
< Wheel Up 
< OS1 
< OS2 
< OS3 
Wheel Right > 
Wheel Left > 
CNTR0 > 
PMSR > 
EMSR0 > 
EMSR1 > 
EMSR2 > 
EMSR3 > 
PID1 > 
PID2 > 
PID3 > 
V
REF
 > 
RESET
 >
 
CNVss > 
Vcc > 
Xin > 
Xout > 
Vss > 
UP-X500V
CIRCUIT DESCRIPTION
5 – 7
5-3-2.Pin list
Pin 
No.
Terminal name
I/O
Description
1.
Wheel Right
I
Right button
2.
Wheel Left
I
Left button
3.
CNTR0 
I
Connected to No.4 pin
4.
EMSR0/PMSR
I
Panel electrode voltage measurement terminal
5.
EMSR1/EMSR0
I
Panel electrode voltage measurement terminal
6.
EMSR2/EMSR1
I
Panel electrode voltage measurement terminal
7.
EMSR3/EMSR2
I
Panel electrode voltage measurement terminal
8.
JPHID/EMSR3
O
HID class selection/panel electrode volt-
age measurement terminal
9.
PID1
O
PID selection terminal
10.
PID2
O
PID selection terminal
11.
PID3
O
PID selection terminal
12.
Vref
-
A/D converter reference voltage input terminal
13.
Reset
I
Reset input terminal
14.
CNVss
-
Connected to VSS
15.
Vcc
-
Power supply input terminal (5V)
16.
Xin
I
Clock input terminal
17.
Xout
O
Clock output terminal
18.
Vss
-
Power supply input terminal (0V)
19.
OS3
I
Home position selection terminal
20.
OS2
I
Home position selection terminal
21.
OS1
I
Home position selection terminal
22.
WheelUP
I
Upward scroll button
23.
WheelDOWN
I
Downward scroll button
24.
JPMODE
I
4/7 wire selection
25.
ModuleDisable
I
Disconnection operation simulation terminal
26.
USBVref
O
USB reference voltage output terminal
27.
PSW3
O
Panel drive switch control output terminal
28.
PSW4
O
Panel drive switch control output terminal
29.
PSW1
O
Panel drive switch control output terminal
30.
PSW2
O
Panel drive switch control output terminal
31.
PSW0
O
Panel drive switch control output terminal
32.
ButtonLeft
I
Left button
33.
ButtonRight
I
Right button
34.
ButtonMiddle
I
Center button
35.
USB D-
I/O USB I/O terminal
36.
USB D+
I/O USB I/O terminal
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