DOWNLOAD Panasonic UF-885 / UF-895 Service Manual ↓ Size: 22.48 MB | Pages: 127 in PDF or view online for FREE

33

LCU/LCE PCB consists of line connection circuit between Telephone / FAX circuit, PSTN and detection circuit of line condition.

1. Line Control

The PSTN line is connected from telephone side to FAX side by CML relay. The relay connects to the Fax side by CML signal
becomes 5V.

2. Automatic Reception

Due to PC2: LCE PCB / PC1: LCE PCB, ringing signal is changed to digital signal (0V and 5V) and it is transfered to System
CPU on FCB PCB. System CPU on FCB PCB confirms Frequency, On/Off timing and changes the PSTN connection from
telephone side to FAX side.

3. Off Hook Detection

Due to loop current during off hook, PC1:LCU / IC1, RL1 or PC2:LCE becomes to 0-Volt and System CPU detects off hook
through the Multiplexer.

4. Dialing

• Dial Pulse Dialing

The circlet consists of the CML relay, PLS relay and their peripheral circlet. This circlet generates dial pulses. The CPU in the
FCB PCB controls all dial pulse generation sequences. It turns relay CML and PLS on and off through API on the FCB PCB.
When the absence of the terminating message is confirmed by the of-hook detector, the CPU turns CML relay ON to develop
loop status (DC loop). After a few seconds, the CPU turns the PLS relay on and off to generator dial pulses making and
breaking the loop.

• DTMF Tone

Modem generates DTMF. The output route is same as FAX transmission signal.

MODEM

ApI

PC2

PC1

CML

PLS

TCK

Ringing

Detector

Line

Telephone

CML

PC1

nCTON

RMCK

RMCS

RMDT

CLK

P/S

Q8

PC2

JP18~23

Country

Code

Jumper

IC2

CML

PLS

TCK

+24V

+24V

+24V

Q1

Q3

Q4

Off-hook
Detector

HYBSR

<MDM>

< LCE >

L : Ring in

H : FAX Side
L : Telephone 

H : Make
L : Break

CN8

CN25

11

11

10

10

7

7

8

8

9

9

5

5

6

6

CMLD

PLSD

14

14

Ringer

Off Hook

Dial Pulse

Loop Relay

TCKD

[DZYNA1436*]

MODEM

PC2

CML

PLS

Ringing

Detector

Line

Telephone

CML

C5

Q2

Off-hook
Detector

HYBSR

< MDM >

< LCU >

PC1

GND

T2

Q1

PC1

nCTON

PLS

CML

+24V

CMLD 5

PLSD 6

PC2

nHKOFF 9

+5V

+5V

L : Hook off
H : On hook 

L : Ring IN 10

H : FAX Side
L : Telephone

CN7

H : Make
L : Break

for Auto Receive

API

[DZYNA1435*]

MODEM

PC1

PC2

CML

PLS

Ringing

Detector

Line

Telephone

CML

C5

Q2

HYBSR

< MDM >

< LCE >

GND

T2

Q1

PC2

nCTON

PLS

CML

+24V

CMLD 5

PLSD 6

PC1

nHKOFF 9

+5V

+5V

L : Hook off
H : On hook 

L : Ring IN 10

H : FAX Side
L : Telephone

CN7

H : Make
L : Break

API

[DZEP000441]

34

Panel block consists of LCD module (not repairable) and Panel CPU, Key matrix and LED on PNL PCB. These are controlled by
one chip CPU (4 bit) on LCD PCB. This CPU is controlled by System CPU on FCB PCB.

1. Panel I/F with System CPU

PTXD, PRXD, PNL CLOCK : Half-duplex transmission is carried out by clock synchronized serial I/F of 3 line type.

2. LED Drive

LED is driven by dynamic drive.

3. Key Scan

Switch condition is detected through matrix line of 8 bit data X 10 line for each 10 ms cycle. This information is transferred to
System CPU when panel CPU receives a request.

4. Calender

The Calendar information is counted up by panel CPU. This information is transferred to System CPU when panel CPU
receives a request. During power off Panel CPU is back up by battery on Panel Block.

• PNLRST

:

System CPU puts out reset signal if there is no response from Panel CPU.

• WAKUP

:

Sleep Mode cancel signal from FCB PCB

• PSAVE

:

Sleep Mode approval signal to FCB PCB

• BZCLK

:

When panel SW is pressed, panel SW sound clock is put out.

• BATLVOL

:

Due to this signal line, System CPU on FCB PCB detects Battery condition.

9

3

2

4

5

1

11

12

10

6

7

8

13

+5V

+5V

KEYIN (7:0)

Key Matrix

LED Matrix

LED (7:0)

SCAN (9:0)

LEDCT (1:0)

To FCB

BATVOL

BATVOL

BAT

TXS

RXS

CKS

BUZ

RES

nPNLTXD

nPNLRXD

nPNLCK

nBZCK

nPNLRST

nPSAVE

nWAKUP

+5V

+5VP

GND

GND

+24V

(NC)

GND

GND

GND

GND

+5V panel

+5VP

+5VP

+5VP

Battery

+3V

8.00 MHz

32.768 KHz

(For RTC)

Battery

for RTC

CPU

TMP87CH00LF

VDD

*RESET

XIN

XOUT

XTIN

XTOUT

COG

Chip

on

Glass

VDD

V0

VSS

DB (7:0)

E

RS

R/W

35

This function is to reduce the power consumption in standby mode. During Sleep Mode, power is not supplied to System Control 
circuit on FCB PCB. It is supplied to Panel PCB and some circuit on FCB PCB.

1. Shifted conditions to Sleep Mode

• Sleep Mode timer is time over (default: 60 minutes).
• During the timer period, there are no TX/RX and no operation from Panel.
• Document sensor ON
• Option PCB (G3, PDL, Printer I/F) is not installed.

2. Recovered conditions from Sleep Mode

• Key input on Panel
• Deferred Communication is time over
• Document sensor ON
• Ringing signal input
• Hook-off (external telephone or Handset: except LCE PCB)

+5VP

+5VP

+5VP

Q204-2

Q206-2

Q203-2

Q202-2

Q202-3

+5VP

+5VP

5V

5V

3V

+5VP

nAPNT

API

nCTONP

nHKOFP

nHSDTP

OPEN

not used

nLPOW

nPSDES

nPSG

Command

3  : L

nPSAVE

nWAKUP

LED

Self-Keep 

Circuit

Option

POW

SNS

NCU

Document
Sensor 

+5VP

Q205 C721

CI Detect

EX-TEL Hook Up 
Detect

Handset Hook Up 
Detect

Sub-CPU, API

+5VP

API

+5VP

API

CPU

+24V

-12V

+5V

+24V / +12V

-12V

+5V / +3.3V

+5VP

WAKUP Circuit

Display Sleep 

Mode

Option
G3 & PDL

Main
CPU

PNL CPU

PA7

P14

P53

P50

Disenable 
Sleep Mode

1  : L

2  : Power
      OFF

4  : L

5  : OFF

5  : OFF

Q200

6  : OFF

36