Panasonic UF-885 / UF-895 Service Manual / Other ▷ View online
45
3.1.6
Power PC 403GCX
68
HRCK
I
FIFO memory read enable clock input pin.
73-80
HMOD7-0
I
FIFO memory data input pin. In modes where FRIP5 uses FIFO memory (other than
notch processing), this signal is input from the FRIP5.
notch processing), this signal is input from the FRIP5.
81-87,90
HMID7-0
O
FIFO memory data output pin.
72
MSCK
O
FRIP5 master clock output pin.
95
OFSG
O
CCD transfer gate clock output pin. Generated from FSG and MSCK.
91
OFCK1
O
CCD shift register clock 1 output pin. Generated from FCK1 and MSCK.
92
OFCK2
O
CCD shift register clock 2 output pin. Generated from FCK1 and MSCK.
93
OFR1
O
CCD reset gate clock 1 output pin. Generated from FR1 and CLKIN0.
94
OFR2
O
CCD reset gate clock 2 output pin. Generated from FR1 and CLKIN0.
39
A/B/C/SWE
O
SRAM WE signal output pin. Generated from WE and RE from FRIP5.
40-43,46-
54
SA12-0
O
SRAM address signal output pin. (for shading, reference pixel memory)
34
VSENA
O
Load image data enable output pin. For notch processing, this signal is generated
in the FIFO memory controller based on the VSEN signal. Otherwise the VSEN signal
is output directly.
in the FIFO memory controller based on the VSEN signal. Otherwise the VSEN signal
is output directly.
35
VSDAA
O
Load image data output pin. For notch processing, the signal is generated in the
FIFO memory controller based on data in the FIFO memory. Otherwise the VSDA sig-
nal is output directly.
FIFO memory controller based on data in the FIFO memory. Otherwise the VSDA sig-
nal is output directly.
100
VENB
I
Load image data enable input pin from SUB CPU1.
99
SBCK
O
SUB CPU1 system clock output pin.
104
XTAL1I
I
Clock transmission for synchronization input pin
105
XTAL1O
O
Clock transmission for synchronization output pin
112
XTAL2I
I
Clock transmission for synchronization input pin
113
XTAL2O
O
Clock transmission for synchronization output pin
117
XTAL3I
I
Clock transmission for synchronization input pin
118
XTAL3O
O
Clock transmission for synchronization output pin
134
XTAL4I
I
Clock transmission for synchronization input pin
135
XTAL4O
O
Clock transmission for synchronization output pin
106
CKI1
I
Synchronization clock input pin
109
CKI2
I
Synchronization clock input pin
116
CKI3
I
Synchronization clock input pin
137
HSYNC
I
Horizontal synchronization input pin from LP
138
VSYNC
I
Vertical synchronization input pin from LP
147
VDO
O
Video data output pin to LP
139
VDOCK
O
Video clock output pin
145
PRDY
I
LP and command relations control signal pin
146
PRNT
O
LP and command relations control signal pin
140
CBSY
O
LP and command relations control signal pin
141
SBSY
I
LP and command relations control signal pin
142
CMD
O
LP and command relations control signal pin
143
STA
I
LP and command relations control signal pin
144
CCLK
O
LP and command relations control signal pin
32
PSDA
I
Data signal input pin from image G/A
33
PSCK
O
Clock signal output pin to image G/A
31
PSRQ
O
Data enable output pin to image G/A
158-174
ZA0-16
O
Address bus for revised data ROM
148-
153,155-
157
ZD0-7
I
Data bus for revised data ROM
20,21,24-
26
A0-4
I
Address bus for system
2-12,15-
19
D0-15
I/O
Data bus for system
28
RD
I
Read signal input pin for system
29
WRL
I
Low write signal for system
30
WRH
I
High write signal for system
175
INT
O
Interrupt request signal to system
27
CS
I
Chip select signal
131
RST
I
Reset signal
125
R
I
PLL input pin
126
VCNT
I
PLL input pin
128
PDO
O
PLL output pin
129,130,1
36
TST0,1,2
I
Test input pin
121-123
SCN0,1,2
I
SCAN test input pin
Pin No.
Pin Name
Type
Description
92
A6
I/O
Address Bus Bit 6. When the 403GCX is bus master, this is an address output from
the 403GCX. When the 403GCX is not bus master, this is an address input from the
external bus master, to determine bank register usage.
the 403GCX. When the 403GCX is not bus master, this is an address input from the
external bus master, to determine bank register usage.
93
A7
I/O
Address Bus Bit 7. See description of A6.
Pin No.
Pin Name
Type
Description
46
94
A8
I/O
Address Bus Bit 8. See description of A6.
95
A9
I/O
Address Bus Bit 9. See description of A6.
96
A10
I/O
Address Bus Bit 10. See description of A6.
97
A11
I/O
Address Bus Bit 11. See description of A6.
98
A12
O
Address Bus Bit 12. When the 403GCX is bus master, this is an address output from
the 403GCX.
the 403GCX.
99
A13
O
Address Bus Bit 13. See description of A12.
103
A14
O
Address Bus Bit 14. See description of A12.
104
A15
O
Address Bus Bit 15. See description of A12.
105
A16
O
Address Bus Bit 16. See description of A12.
106
A17
O
Address Bus Bit 17. See description of A12.
107
A18
O
Address Bus Bit 18. See description of A12.
108
A19
O
Address Bus Bit 19. See description of A12.
109
A20
O
Address Bus Bit 20. See description of A12.
110
A21
O
Address Bus Bit 21. See description of A12.
112
A22
I/O
Address Bus Bit 22. When the 403GCX is bus master, this is an address output from
the 403GCX. When the 403GCX is not bus master, this is an address input from the
external bus master, to determine page crossings.
the 403GCX. When the 403GCX is not bus master, this is an address input from the
external bus master, to determine page crossings.
113
A23
I/O
Address Bus Bit 23. See description of A22.
114
A24
I/O
Address Bus Bit 24. See description of A22.
115
A25
I/O
Address Bus Bit 25. See description of A22.
116
A26
I/O
Address Bus Bit 26. See description of A22.
117
A27
I/O
Address Bus Bit 27. See description of A22.
118
A28
I/O
Address Bus Bit 28. See description of A22.
119
A29
I/O
Address Bus Bit 29. See description of A22.
139
AMuxCAS
O
DRAM External Address Multiplexer Select. AMuxCAS controls the select logic on an
external multiplexer. If AMuxCAS is low, the multiplexer should select the row
address for the DRAM and when AMuxCAS is 1, the multiplexer should select the
column address.
external multiplexer. If AMuxCAS is low, the multiplexer should select the row
address for the DRAM and when AMuxCAS is 1, the multiplexer should select the
column address.
11
BootW
I
Boot-up ROM Width Select. BootW is sampled while the Reset pin is active and
again after Reset becomes inactive to determine the width of the boot-up ROM. If
this pin is tied to logic 0 when sampled on reset, an 8-bit boot width is assumed.
If BootW is tied to 1, a 32-bit boot width is assumed. For 16-bit boot widths,
this pin should be tied to the RESET pin.
again after Reset becomes inactive to determine the width of the boot-up ROM. If
this pin is tied to logic 0 when sampled on reset, an 8-bit boot width is assumed.
If BootW is tied to 1, a 32-bit boot width is assumed. For 16-bit boot widths,
this pin should be tied to the RESET pin.
12
BusError
I
Bus Error Input. A logic 0 input to the BusError pin by an external device sig-
nals to the 403GCX that an error occurred on the bus transaction. BusError is
only sampled during the data transfer cycle or the last wait cycle of the trans-
fer.
nals to the 403GCX that an error occurred on the bus transaction. BusError is
only sampled during the data transfer cycle or the last wait cycle of the trans-
fer.
135
BusReq/
DMADXFER
O
Bus Request. While HoldAck is active, BusReq is active when the 403GCX has a bus
operation pending and needs to regain control of the bus.
DMA Data Transfer. When HoldAck is not active, DMADXFER indicates a valid data
transfer cycle. For DMA use, DMADXFER conrols burst-mode fly-by DMA transfers
between memory and peripherals. DMADXFER is not meaningful unless a DMA Acknowl-
edge signal (DMAA0:3) is active. For transfer rates slower than one transfer per
cycle, DMADXFER is active for one cycle when one transfer is complete and the
next one starts. For transfer rates of one transfer per cycle, DMADXFER remains
active throughout the transfer.
operation pending and needs to regain control of the bus.
DMA Data Transfer. When HoldAck is not active, DMADXFER indicates a valid data
transfer cycle. For DMA use, DMADXFER conrols burst-mode fly-by DMA transfers
between memory and peripherals. DMADXFER is not meaningful unless a DMA Acknowl-
edge signal (DMAA0:3) is active. For transfer rates slower than one transfer per
cycle, DMADXFER is active for one cycle when one transfer is complete and the
next one starts. For transfer rates of one transfer per cycle, DMADXFER remains
active throughout the transfer.
142
CAS0
O
DRAM Column Address Select 0. CAS0 is used with byte 0 of all DRAM banks.
143
CAS1
O
DRAM Column Address Select 1. CAS1 is used with byte 1 of all DRAM banks.
144
CAS2
O
DRAM Column Address Select 2. CAS2 is used with byte 2 of all DRAM banks.
145
CAS3
O
DRAM Column Address Select 3. CAS3 is used with byte 3 of all DRAM banks.
36
CINT
I
Critical Interrupt. Ton initiate a critical interrupt, the user must maintain a
logic 0 on the CINT pin for a minimum of one SysClk clock cycle followed by a
logic 1 on the CINT pin for at least one SysClk cycle.
logic 0 on the CINT pin for a minimum of one SysClk clock cycle followed by a
logic 1 on the CINT pin for at least one SysClk cycle.
155
CS0
O
SRAM Chip Select 0. Bank register 0 controls an SRAM bank, CS0 is the chip select
for that bank.
for that bank.
154
CS1
O
SRAM Chip Select 1. See description of CS0 but controls bank 1.
153
CS2
O
SRAM Chip Select 2. See description of CS0 but controls bank 2.
152
CS3
O
SRAM Chip Select 3. See description of CS0 but controls bank 3.
151
CS4/RAS3
O
Chip Select 4/ DRAM Row Address Select 3. When bank register 4 is configured to
control an SRAM bank, CS4/RAS3 functions as a chip select. When bank register 4
is configured to control a DRAM bank, CS4/RAS3 is the row address select for that
bank.
control an SRAM bank, CS4/RAS3 functions as a chip select. When bank register 4
is configured to control a DRAM bank, CS4/RAS3 is the row address select for that
bank.
148
CS5/RAS2
O
Chip Select 5/ DRAM Row Address Select 2. See description of CS4/RAS3 but con-
trols bank 5.
trols bank 5.
147
CS6/RAS1
O
Chip Select 6/ DRAM Row Address Select 1. See description of CS4/RAS3 but con-
trols bank 6.
trols bank 6.
146
CS7/RAS0
O
Chip Select 7/ DRAM Row Address Select 0. See description of CS4/RAS3 but con-
trols bank 7.
trols bank 7.
42
D0
I/O
Data bus bit 0 (Most significant bit)
43
D1
I/O
Data bus bit 1.
44
D2
I/O
Data bus bit 2.
45
D3
I/O
Data bus bit 3.
46
D4
I/O
Data bus bit 4.
47
D5
I/O
Data bus bit 5.
48
D6
I/O
Data bus bit 6.
51
D7
I/O
Data bus bit 7.
52
D8
I/O
Data bus bit 8.
53
D9
I/O
Data bus bit 9.
54
D10
I/O
Data bus bit 10.
Pin No.
Pin Name
Type
Description
47
55
D11
I/O
Data bus bit 11.
56
D12
I/O
Data bus bit 12.
57
D13
I/O
Data bus bit 13.
58
D14
I/O
Data bus bit 14.
62
D15
I/O
Data bus bit 15.
63
D16
I/O
Data bus bit 16.
64
D17
I/O
Data bus bit 17.
65
D18
I/O
Data bus bit 18.
66
D19
I/O
Data bus bit 19.
67
D20
I/O
Data bus bit 20.
68
D21
I/O
Data bus bit 21.
71
D22
I/O
Data bus bit 22.
72
D23
I/O
Data bus bit 23.
73
D24
I/O
Data bus bit 24.
74
D25
I/O
Data bus bit 25.
75
D26
I/O
Data bus bit 26.
76
D27
I/O
Data bus bit 27.
77
D28
I/O
Data bus bit 28.
78
D29
I/O
Data bus bit 29.
79
D30
I/O
Data bus bit 30.
82
D31
I/O
Data bus bit 31.
156
B4
O
DMA Channel 0 Acknowledge. DMAA0 has an active level when a transaction is taking
place between the 403GCX and a peripheral.
place between the 403GCX and a peripheral.
157
A3
O
DMA Channel 1 Acknowledge. See description of DMAA0.
158
C3
O
DMA Channel 2 Acknowledge. See description of DMAA0.
159
B3
O
DMA Channel 3 Acknowledge / External Master Transfer Acknowledge. When the 403GCX
is bus master, this signal is DMAA3; see description of DMAA0. When the 403GCX is
not the bus master, this signal is XACK, an output from the 403GCX which has an
active level when data is valid during an external bus master transaction.
is bus master, this signal is DMAA3; see description of DMAA0. When the 403GCX is
not the bus master, this signal is XACK, an output from the 403GCX which has an
active level when data is valid during an external bus master transaction.
2
B2
I
DMA Channel 0 Request. External devices request a DMA transfer on channel 0 by
putting a logic 0 on DMAR0.
putting a logic 0 on DMAR0.
3
B1
I
DMA Channel 1 Request. See description of DMAR0.
4
C2
I
DMA Channel 2 Request. See description of DMAR0.
5
C1
I
DMA Channel 3 Request. When the 403GCX is the bus master, external devices
request a DMA transfer on channel 3 by putting a logic 0 on DMAR3. See descrip-
tion of DMAR0. When the 403GCX is not the bus master, DMAR3 is used as the XREQ
input. The external bus master places a logic 0 on XREQ to initiate a transfer to
the DRAM controlled by the 403GCX DRAM controller.
request a DMA transfer on channel 3 by putting a logic 0 on DMAR3. See descrip-
tion of DMAR0. When the 403GCX is not the bus master, DMAR3 is used as the XREQ
input. The external bus master places a logic 0 on XREQ to initiate a transfer to
the DRAM controlled by the 403GCX DRAM controller.
137
D9
O
DRAM Output Enable. DRAMOE has an active level when either the 403GCX or an
external bus master is reading from a DRAM bank. This signal enables the selected
DRAM bank to drive the data bus.
external bus master is reading from a DRAM bank. This signal enables the selected
DRAM bank to drive the data bus.
90
GND
Gound. All ground pins must be used.
101
GND
Gound. All ground pins must be used.
102
GND
Gound. All ground pins must be used.
111
GND
Gound. All ground pins must be used.
121
GND
Gound. All ground pins must be used.
130
GND
Gound. All ground pins must be used.
141
GND
Gound. All ground pins must be used.
150
GND
Gound. All ground pins must be used.
9
Halt
I
Halt from external debugger, active low.
134
HoldAck
O
Hold Acknowledge. HoldAck outputs a logic 1 when the 403GCX relinquishes its
external buses to an external bus master. HoldAck outputs a logic 0 when the
403GCX regains control of the bus.
external buses to an external bus master. HoldAck outputs a logic 0 when the
403GCX regains control of the bus.
14
HoldReq
I
Hold Request. External bus masters can request the 403GCX bus by placing a logic
1 on this pin. The external bus master relinquishes the bus to the 403GCX by dis-
serting HoldReq.
1 on this pin. The external bus master relinquishes the bus to the 403GCX by dis-
serting HoldReq.
31
INT0
I
Interrupt 0. INT 0 is an interrupt input to the 403GCX and users may program the
pin to be either edge-triggered or level-triggered and may also program the
polarity to be active high or active low. The IOCR contains the bits necessary to
program the trigger type and polarity.
pin to be either edge-triggered or level-triggered and may also program the
polarity to be active high or active low. The IOCR contains the bits necessary to
program the trigger type and polarity.
32
INT1
I
Interrupt 1. See description of INT0.
33
INT2
I
Interrupt 2. See description of INT0.
34
INT3
I
Interrupt 3. See description of INT0.
35
INT4
I
Interrupt 4. See description of INT0.
39
IVR
I
Reserved for manufacturing test. Tied high for normal operation.
126
OE/XSize1/
Blast
O/I/O
Output Enable / External Master Transfer Size 1. When the 403GCX is bus master,
OE enables the selected SRAMs to drive the data bus. The timing parameters of OE
relative to the chip select, CS, are programmable via bits in the 403GCX bank
registers. When the 403GCX is not bus master, OE/XSize1 is used as one of two
external transfer size input bits, XSize0:1. In Byte Enable mode, Burst Last
(BLast) goes active to indicate the last transfer of a memory access, whether
burst or nonburst.
OE enables the selected SRAMs to drive the data bus. The timing parameters of OE
relative to the chip select, CS, are programmable via bits in the 403GCX bank
registers. When the 403GCX is not bus master, OE/XSize1 is used as one of two
external transfer size input bits, XSize0:1. In Byte Enable mode, Burst Last
(BLast) goes active to indicate the last transfer of a memory access, whether
burst or nonburst.
13
Ready
I
Ready. Ready is used to insert externally generated (device-paced) wait states
into bus transactions. The Ready pin is enabled via the Ready Enable bit in
403GCX bank registers.
into bus transactions. The Ready pin is enabled via the Ready Enable bit in
403GCX bank registers.
27
RecvD
I
Serial Port Receive Data.
138
DRAMWE
O
DRAM Write Enable. DRAMWE has an active level when either the 403GCX or an exter-
nal bus master is writing to a DRAM bank.
nal bus master is writing to a DRAM bank.
Pin No.
Pin Name
Type
Description
48
28
DSR/CTS
I
Data Set Ready / Clear to Send. The function of this pin as either DSR or CTS is
selectable via the Serial Port Configuration bit in the IOCR.
selectable via the Serial Port Configuration bit in the IOCR.
88
DTR/RTS
O
Data Terminal Ready / Request to Send. The function of this pin as either DTR or
RTS is selectable via the Serial Port Configuration bit in the IOCR.
RTS is selectable via the Serial Port Configuration bit in the IOCR.
128
EOT0/TC0
I/O
End of Transfer 0 / Terminal Count 0. The function of the EOT0/TC0 is controlled
via the EOT/TC bit in the DMA Channel 0 Control Register. When EOT0/TC0 is con-
figured as an End of Transfer pin, external users may stop a DMA transfer by
placing a logic 0 on this input pin. When configured as a Terminal Count pin, the
403GCX signals the completion of a DMA transfer by placing a logic 0 on this pin.
via the EOT/TC bit in the DMA Channel 0 Control Register. When EOT0/TC0 is con-
figured as an End of Transfer pin, external users may stop a DMA transfer by
placing a logic 0 on this input pin. When configured as a Terminal Count pin, the
403GCX signals the completion of a DMA transfer by placing a logic 0 on this pin.
131
EOT1/TC1
I/O
End of Transfer 1 / Terminal Count 1. See description of EOT0/TC0.
132
EOT2/TC2
I/O
End of Transfer 2 / Terminal Count 2. See description of EOT0/TC0.
133
EOT3/TC3/
XSize0
I/O
End of Transfer 3 / Terminal Count 3 / External Master Transfer Size 0. When the
403GCX is bus master, this pin has the same function as EOT0/TC0.
When the 403GCX is not bus master, EOT3/TC3/XSize0 is used as one of two external
transfer size input bits, XSize0:1.
403GCX is bus master, this pin has the same function as EOT0/TC0.
When the 403GCX is not bus master, EOT3/TC3/XSize0 is used as one of two external
transfer size input bits, XSize0:1.
136
Error
O
System Error. Error goes to a logic 1 whenever a machine check error is detected
in the 403GCX. The Error pin then remains a logic 1 until the machine check error
is cleared in the Exception Syndrome Register and/or Bus Error syndrome Register.
in the 403GCX. The Error pin then remains a logic 1 until the machine check error
is cleared in the Exception Syndrome Register and/or Bus Error syndrome Register.
1
GND
Ground. All ground pins must be used.
10
GND
Ground. All ground pins must be used.
15
GND
Ground. All ground pins must be used.
29
GND
Ground. All ground pins must be used.
30
GND
Ground. All ground pins must be used.
41
GND
Ground. All ground pins must be used.
50
GND
Ground. All ground pins must be used.
59
GND
Ground. All ground pins must be used.
60
GND
Ground. All ground pins must be used.
70
GND
Ground. All ground pins must be used.
81
GND
Ground. All ground pins must be used.
91
Reset
I/O
Reset. A logic 0 input placed on this pin for one SysClk cycle causes the 403GCX
to begin a system reset. When a system reset is invoked, the Reset pin becomes a
logic 0 output for 2048 SysClk cycles.
to begin a system reset. When a system reset is invoked, the Reset pin becomes a
logic 0 output for 2048 SysClk cycles.
127
R/W
I/O
Read / Write. When the 403GCX is bus master, R/W is an output which is high when
data is read from memory and low when data is written to memory.
When the 403GCX is not bus master, R/W is an input from the external bus master
which indicates the direction of data transfer.
data is read from memory and low when data is written to memory.
When the 403GCX is not bus master, R/W is an input from the external bus master
which indicates the direction of data transfer.
26
SerClk
I
Serial Port Clock. Through the Serial Port Clock Source bit in the Input/Output
Configuration register (IOCR), users may choose the serial port clock source from
either the input on the SerClk pin or processor SysClk. The maximum allowable
input frequency into SerClk is half the SysClk frequency.
Configuration register (IOCR), users may choose the serial port clock source from
either the input on the SerClk pin or processor SysClk. The maximum allowable
input frequency into SerClk is half the SysClk frequency.
22
SysClk
I
SysClk is the processor system clock input. The 403GCX can also be programmed to
operate at a 2X internal clock rate while the external bus interface runs at the
SysClk input rate.
operate at a 2X internal clock rate while the external bus interface runs at the
SysClk input rate.
6
TCK
I
JTAG Test Clock Input. TCK is the clock source for the 403GCX test access port
(TAP). The maximum clock rate into the TCK pin is one half of the processor
SysClk clock rate.
(TAP). The maximum clock rate into the TCK pin is one half of the processor
SysClk clock rate.
8
TDI
I
Test Data In. The TDI is used to input serial data into the TAP. When the TAP
enables the use of the TDI pin, the TDI pin is sampled on the rising edge of TCK
and this data is input to the selected TAP shift register.
enables the use of the TDI pin, the TDI pin is sampled on the rising edge of TCK
and this data is input to the selected TAP shift register.
16
TDO
O
Test Data Output. TDO is used to transmit data from the 403GCX TAP. Data from the
selected TAP shift register is shifted out on TDO.
selected TAP shift register is shifted out on TDO.
23
TestA
I
Reserved for manufacturing test. Tied low for normal operation.
24
TestB
I
Reserved for manufacturing test. Tied high for normal operation.
37
TestC/Hold-
Pri
I
TestC. Reserved for manufacturing test during the reset interval. While Reset is
active, this signal should be tied low for normal operation. HoldReq Priority.
When Reset is not active, this signal is sampled to determine the priority of the
external bus master signal HoldReq. If HoldPri = 0 then the HoldReq signal is
considered high priority, otherwise HoldReq is considered low priority.
active, this signal should be tied low for normal operation. HoldReq Priority.
When Reset is not active, this signal is sampled to determine the priority of the
external bus master signal HoldReq. If HoldPri = 0 then the HoldReq signal is
considered high priority, otherwise HoldReq is considered low priority.
38
TestD
I
Reserved for manufacturing test. Tied low for normal operation.
25
TimerClk
I
Timer Facility Clock. Through the Timer Clock Source bit in the Input/Output Con-
figuration register (IOCR), users may choose the clock source for the Timer
facility from either the input on the TimerClk pin or processor CoreClk. The max-
imum input frequency into TimerClk is half the CoreClk frequency.
figuration register (IOCR), users may choose the clock source for the Timer
facility from either the input on the TimerClk pin or processor CoreClk. The max-
imum input frequency into TimerClk is half the CoreClk frequency.
122
WBE0/A4/BE0
O/I/O
Write Byte Enable 0 / Address Bus Bit 4 / Byte Enable 0. When the 403GCX is bus
master, the write byte enable outputs, WBE0:3, select the active byte(s) in a
memory write access to SRAM. The byte enables can also be programmed as read/
write byte enables, depending on the mode set in the IOCR. Note 3 on page 35 sum-
marizes the functional and timing differences in these signals when programmed as
read/write byte enables. For 8-bit memory regions, WBE2 and WBE3 become address
bits 30 and 31 and WBE0 is the byte-enable line. For 16-bit memory regions, WBE2
and WBE3 become address bits 30 and 31 and WBE0 and WBE1 are the high byte and low
byte enables, respectively. For 32-bit memory regions, WBE0:3 are byte enables
for bytes 0-3 on the data bus, respectively. When the 403GCX is not bus master,
WBE0:1 are used as the A4:5 inputs (for bank register selection) and WBE2:3 are
used as the A30:31 inputs (for byte selection and page crossing detection).
master, the write byte enable outputs, WBE0:3, select the active byte(s) in a
memory write access to SRAM. The byte enables can also be programmed as read/
write byte enables, depending on the mode set in the IOCR. Note 3 on page 35 sum-
marizes the functional and timing differences in these signals when programmed as
read/write byte enables. For 8-bit memory regions, WBE2 and WBE3 become address
bits 30 and 31 and WBE0 is the byte-enable line. For 16-bit memory regions, WBE2
and WBE3 become address bits 30 and 31 and WBE0 and WBE1 are the high byte and low
byte enables, respectively. For 32-bit memory regions, WBE0:3 are byte enables
for bytes 0-3 on the data bus, respectively. When the 403GCX is not bus master,
WBE0:1 are used as the A4:5 inputs (for bank register selection) and WBE2:3 are
used as the A30:31 inputs (for byte selection and page crossing detection).
123
WBE1/A5/BE1
O/I/O
Write Byte Enable 1 / Address Bus Bit 5 / Byte Enable 1. See description of WBE0
/ A4 above.
/ A4 above.
124
WBE2/A30/BE2
O/I/O
Write Byte Enable 2 / Address Bus Bit 30 / Byte Enable 2. See description of WBE0
/ A4 above.
/ A4 above.
125
WBE3/A31/BE3
O/I/O
Write Byte Enable 3 / Address Bus Bit 31 / Byte Enable 3. See description of WBE0
/ A4 above.
/ A4 above.
87
XmitD
O
Serial port transmit data.
Pin No.
Pin Name
Type
Description
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