DOWNLOAD Panasonic UF-885 / UF-895 Service Manual ↓ Size: 22.48 MB | Pages: 127 in PDF or view online for FREE

Model
UF-885 UF-895
Pages
127
Size
22.48 MB
Type
PDF
Document
Service Manual / Other
Brand
Device
Fax / LASER
File
uf-885-uf-895.pdf
Date
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41
136
D8
I/O
TTL level Input/Output with pull-down resistance (IoI=3mA)
137
D9
I/O
TTL level Input/Output with pull-down resistance (IoI=3mA)
138
GND
O
Ground
139
D10
I/O
TTL level Input/Output with pull-down resistance (IoI=3mA)
140
D11
I/O
TTL level Input/Output with pull-down resistance (IoI=3mA)
141
D12
I/O
TTL level Input/Output with pull-down resistance (IoI=3mA)
142
D13
I/O
TTL level Input/Output with pull-down resistance (IoI=3mA)
143
D14
I/O
TTL level Input/Output with pull-down resistance (IoI=3mA)
144
D15
I/O
TTL level Input/Output with pull-down resistance (IoI=3mA)
145
GND
O
Ground
146
A0
I
TTL level input with pull-down resistance
147
A1
I
TTL level input with pull-down resistance
148
A2
I
TTL level input with pull-down resistance
149
A3
I
TTL level input with pull-down resistance
150
A4
I
TTL level input with pull-down resistance
151
A5
I
TTL level input with pull-down resistance
152
A6
I
TTL level input with pull-down resistance
153
A7
I
TTL level input with pull-down resistance
154
A8
I
TTL level input with pull-down resistance
155
A9
I
TTL level input with pull-down resistance
156
A10
I
TTL level input with pull-down resistance
157
A11
I
TTL level input with pull-down resistance
158
A12
I
TTL level input with pull-down resistance
159
A13
I
TTL level input with pull-down resistance
160
A14
I
TTL level input with pull-down resistance
161
A15
I
TTL level input with pull-down resistance
162
A16
I
TTL level input with pull-down resistance
163
VCC
I
Power
164
A17
I
TTL level input with pull-down resistance
165
A18
I
TTL level input with pull-down resistance
166
GND
I
Ground
167
A19
I
TTL level input with pull-down resistance
168
A20
I
TTL level input with pull-down resistance
169
A21
I
TTL level input with pull-down resistance
170
NRD
I
TTL level input
171
NWRL
I
TTL level input
172
NWRH
I
TTL level input
173
NRSTIN
I
TTL level input
174
T
-
For diagnostic pin
175
CPUCLK
I
TTL level input
176
W
-
For diagnostic pin
177
VCC
I
Power
178
NCS0
I
TTL level input
179
NCS1
I
TTL level input
180
GND
I
Ground
181
VCC
I
Power
182
NCS2
I
TTL level input
183
NCS3
I
TTL level input
184
GND
O
Ground
185
NWAIT4
I
TTL level input
186
NWDTOVF
I
TTL level input
187
OUT3V1
O
Triple state output (IoI=2mA)
188
OUT3V2
O
Triple state output (IoI=2mA)
189
OUT3V3
O
Triple state output (IoI=2mA)
190
OUT3V4
O
Triple state output (IoI=2mA)
191
OUT3V5
O
Triple state output (IoI=2mA)
192
OUT3V6
O
Triple state output (IoI=2mA)
193
OUT3V7
O
Triple state output (IoI=2mA)
194
OUT3V8
O
Triple state output (IoI=2mA)
195
VCC
O
Power
196
OUT3V9
O
Triple state output (IoI=2mA)
197
OUT3V10
O
Triple state output (IoI=2mA)
198
GND
O
Ground
199
NCS10
O
Triple state output (IoI=2mA)
200
NCS11
O
Triple state output (IoI=2mA)
201
NCS20
O
Triple state output (IoI=2mA)
202
NCS21
O
Triple state output (IoI=2mA)
203
NCS23
O
Triple state output (IoI=2mA)
204
NCS30
O
Triple state output (IoI=2mA)
205
NCS31
O
Triple state output (IoI=2mA)
206
NCS0E
O
Triple state output (IoI=2mA)
207
NCS0F0
O
Triple state output (IoI=2mA)
208
NCS0F1
O
Triple state output (IoI=2mA)
209
VCC
O
Power
Pin No.
Pin Name
Type
Description
42
3.1.4
PEC (Picture Editing Controller)
210
NCS0G
O
Triple state output (IoI=2mA)
211
NIOWR
O
Triple state output (IoI=3mA)
212
GND
O
Ground
213
NDREQ0
O
Triple state output (IoI=2mA)
214
NDREQ1
O
Triple state output (IoI=2mA)
215
NBREQ
O
Triple state output (IoI=2mA)
216
NWAIT
O
Triple state output (IoI=2mA)
217
NRST
O
Output (IoI=3mA)
218
NSCI3INT
O
Triple state output (IoI=2mA)
219
NSCI2INT
O
Triple state output (IoI=2mA)
220
NIRQOUT
O
Triple state output (IoI=2mA)
221
NMIR3
I
TTL level input
222
MIR5
I
TTL level input
223
VCC
I
Power
224
NMIR7
I
TTL level input
225
NMIR8
I
TTL level input
226
GND
I
Ground
227
NMIR9
I
TTL level input
228
NMIR10
I
TTL level input
229
NMIR11
I
TTL level input
230
IN3V1
I
TTL level input
231
DRAK0
I
TTL level input with pull-down resistance
232
DRAK1
I
TTL level input with pull-down resistance
233
DACK0
I
TTL level input with pull-down resistance
234
DACK1
I
TTL level input with pull-down resistance
235
NBACK
I
TTL level input
236
GND
I
Ground
237
VCC
I
Power
238
VCC
I
Power
239
OUT5V1
O
Output (IoI=4mA)
240
GND
O
Ground
Pin No.
Pin Name
Type
Description
2
XIN
I/O
System clock oscillator pin
4
XOUT
I
System clock oscillator pin
-
CKIN
O
Clock input pin
5
CKOUT
I
System clock output pin
-
*RST
O
Reset input pin
151
*CS
I
Main system control signal pin
152
*IORD
I
Main system control signal pin
153
*IOWR
I
Main system control signal pin
-
IOA1
I
Main system address signal pin
-
IOA2
I
Main system address signal pin
-
IOA3
I
Main system address signal pin
-
IOA4
I
Main system address signal pin
-
IOA5
I
Main system address signal pin
-
IOA6
I
Main system address signal pin
-
IOD0
I/O
Main system data signal pin
-
IOD1
I/O
Main system data signal pin
-
IOD2
I/O
Main system data signal pin
-
IOD3
I/O
Main system data signal pin
-
IOD4
I/O
Main system data signal pin
-
IOD5
I/O
Main system data signal pin
-
IOD6
I/O
Main system data signal pin
-
IOD7
I/O
Main system data signal pin
-
IOD8
I/O
Main system data signal pin
-
IOD9
I/O
Main system data signal pin
-
IOD10
I/O
Main system data signal pin
-
IOD11
I/O
Main system data signal pin
-
IOD12
I/O
Main system data signal pin
-
IOD13
I/O
Main system data signal pin
-
IOD14
I/O
Main system data signal pin
155
*INT0
O
Interrupt request output pin
156
*INT1
O
Interrupt request output pin
157
*INT2
O
Interrupt request output pin
162
-IHREQ
I
SGCP Image bus control signal pin
163
-IHACK
O
SGCP Image bus control signal pin
170
IA1
O
SGCP Image buffer address signal pin
171
IA2
O
SGCP Image buffer address signal pin
172
IA3
O
SGCP Image buffer address signal pin
Pin No.
Pin Name
Type
Description
43
173
IA4
O
SGCP Image buffer address signal pin
174
IA5
O
SGCP Image buffer address signal pin
175
IA6
O
SGCP Image buffer address signal pin
178
IA7
O
SGCP Image buffer address signal pin
179
IA8
O
SGCP Image buffer address signal pin
180
IA9
O
SGCP Image buffer address signal pin
181
IA10
O
SGCP Image buffer address signal pin
182
IA11
O
SGCP Image buffer address signal pin
184
IA12
O
SGCP Image buffer address signal pin
185
IA13
O
SGCP Image buffer address signal pin
186
IA14
O
SGCP Image buffer address signal pin
187
IA15
O
SGCP Image buffer address signal pin
188
IA16
O
SGCP Image buffer address signal pin
-
IA17
O
SGCP Image buffer address signal pin
191
ID0
I/O
SGCP Image buffer data signal pin
192
ID1
I/O
SGCP Image buffer data signal pin
193
ID2
I/O
SGCP Image buffer data signal pin
194
ID3
I/O
SGCP Image buffer data signal pin
195
ID4
I/O
SGCP Image buffer data signal pin
196
ID5
I/O
SGCP Image buffer data signal pin
197
ID6
I/O
SGCP Image buffer data signal pin
198
ID7
I/O
SGCP Image buffer data signal pin
199
ID8
I/O
SGCP Image buffer data signal pin
202
ID9
I/O
SGCP Image buffer data signal pin
203
ID10
I/O
SGCP Image buffer data signal pin
204
ID11
I/O
SGCP Image buffer data signal pin
205
ID12
I/O
SGCP Image buffer data signal pin
206
ID13
I/O
SGCP Image buffer data signal pin
207
ID14
I/O
SGCP Image buffer data signal pin
208
ID15
I/O
SGCP Image buffer data signal pin
167
*IMR
O
SGCP Image buffer address signal pin
168
*IMW
O
SGCP Image buffer address signal pin
166
*IME
I
SGCP Image buffer address signal pin
8
SA0
O
Recording Image buffer address signal pin
9
SA1
O
Recording Image buffer address signal pin
11
SA2
O
Recording Image buffer address signal pin
12
SA3
O
Recording Image buffer address signal pin
13
SA4
O
Recording Image buffer address signal pin
14
SA5
O
Recording Image buffer address signal pin
16
SA6
O
Recording Image buffer address signal pin
17
SA7
O
Recording Image buffer address signal pin
18
SA8
O
Recording Image buffer address signal pin
20
SA9
O
Recording Image buffer address signal pin
21
SA10
O
Recording Image buffer address signal pin
22
SA11
O
Recording Image buffer address signal pin
23
SA12
O
Recording Image buffer address signal pin
24
SA13
O
Recording Image buffer address signal pin
25
SA14
O
Recording Image buffer address signal pin
28
SA15
O
Recording Image buffer address signal pin
29
SD0
I/O
Recording Image buffer data signal pin
30
SD1
I/O
Recording Image buffer data signal pin
31
SD2
I/O
Recording Image buffer data signal pin
32
SD3
I/O
Recording Image buffer data signal pin
33
SD4
I/O
Recording Image buffer data signal pin
35
SD5
I/O
Recording Image buffer data signal pin
36
SD6
I/O
Recording Image buffer data signal pin
37
SD7
I/O
Recording Image buffer data signal pin
6
*SRD
O
Recording Image buffer control signal pin
7
*SWR
O
Recording Image buffer control signal pin
93
*VSEN
I
FRIP Interface
94
*VSCK
I
FRIP Interface
95
*VSDA
I
FRIP Interface
98
-PSRQ
I
IPC Interface
99
*PSCK
I
IPC Interface
100
*PSDA
O
IPC Interface
51
MA0
O
Image memory address signal pin
52
MA1
O
Image memory address signal pin
53
MA2
O
Image memory address signal pin
54
MA3
O
Image memory address signal pin
55
MA4
O
Image memory address signal pin
56
MA5
O
Image memory address signal pin
57
MA6
O
Image memory address signal pin
58
MA7
O
Image memory address signal pin
59
MA8
O
Image memory address signal pin
Pin No.
Pin Name
Type
Description
44
3.1.5
IPC (Image Process Controller)
62
MA9
O
Image memory address signal pin
63
MA10
O
Image memory address signal pin
64
MA11
O
Image memory address signal pin
65
MD0
I/O
Image memory data signal pin
66
MD1
I/O
Image memory data signal pin
67
MD2
I/O
Image memory data signal pin
68
MD3
I/O
Image memory data signal pin
69
MD4
I/O
Image memory data signal pin
70
MD5
I/O
Image memory data signal pin
71
MD6
I/O
Image memory data signal pin
74
MD7
I/O
Image memory data signal pin
75
MD8
I/O
Image memory data signal pin
76
MD9
I/O
Image memory data signal pin
77
MD10
I/O
Image memory data signal pin
78
MD11
I/O
Image memory data signal pin
87
MD12
I/O
Image memory data signal pin
88
MD13
I/O
Image memory data signal pin
89
MD14
I/O
Image memory data signal pin
90
MD15
I/O
Image memory data signal pin
41
*RAS0
O
Image memory control signal pin
42
*RAS1
O
Image memory control signal pin
44
*RAS2
O
Image memory control signal pin
45
*RAS3
O
Image memory control signal pin
46
*RAS4
O
Image memory control signal pin
47
*RAS5
O
Image memory control signal pin
49
*CAS
O
Image memory control signal pin
-
*DRD
O
Image memory control signal pin
-
*DWR
O
Image memory control signal pin
91
-HLDRQ
I
Image memory bus control signal pin
92
-HLDAK
O
Image memory bus control signal pin
101
LD0
I
PDL image bus data signal pin
102
LD1
I
PDL image bus data signal pin
103
LD2
I
PDL image bus data signal pin
104
LD3
I
PDL image bus data signal pin
105
LD4
I
PDL image bus data signal pin
106
LD5
I
PDL image bus data signal pin
108
LD6
I
PDL image bus data signal pin
109
LD7
I
PDL image bus data signal pin
110
LD8
I
PDL image bus data signal pin
111
LD9
I
PDL image bus data signal pin
112
LD10
I
PDL image bus data signal pin
113
LD11
I
PDL image bus data signal pin
115
LD12
I
PDL image bus data signal pin
116
LD13
I
PDL image bus data signal pin
117
LD14
I
PDL image bus data signal pin
118
LD15
I
PDL image bus data signal pin
120
PDLRQ
I
PDL image bus control signal pin
121
*PDLAK
O
PDL image bus control signal pin
122
*PDLRD
O
PDL image bus control signal pin
-
-TEST
I
Test terminal
-
VCC1
-
Power terminal (+3.3V)
-
VCC2
-
Power terminal (+5V)
-
GND
-
Ground terminal
Pin No.
Pin Name
Type
Description
101
CLKIN0
I
System clock input pin. Used for external system clock signal for read.
98
FSG
I
CCD transfer gate clock input pin.
96
FCK1
I
CCD shift register clock 1 input pin.
97
FR1
I
CCD reset gate clock input pin.
62
VSEN
I
Load image data enable input pin.
64
VSDA
I
Load image data input pin.
63
VSCK
I
Load image data transfer clock input pin.
56
MRST
I
SRAM address counter reset input pin. Reset count at start of shading processing.
55
MACK
I
SRAM address count-up clock input pin.
57
HMWE
I
WE signal input pin for SRAM from FRIP5.
61
A/B/C/SRE
I
RE signal input pin for SRAM from FRIP5.
71
HFWE
I
FIFO memory write enable input pin.
70
HRSTW
I
FIFO memory write enable reset input pin.
69
HRSTR
I
FIFO memory read enable reset input pin.
65
HWCK
I
FIFO memory write enable clock input pin.
Pin No.
Pin Name
Type
Description
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