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21

Image data circuit (include Page Memory circuit) is independent of System circuit due to high speed scanning and printing.
Due to this, all image data is managed by Image Data circuit. And after coding by Image Codec (SGCP), the coded data is 
transferred to I/O bus & System data bus.

PEC (Gate Array) has following function.

• DRAM (Page Memory) Control

Generate control signal and refresh signal for Page Memory during power on.

• SRAM (Line Memory) Control

Control SRAM as data buffer during following DMA period
Page Memory(DRAM) 

→

  Image SGCP

• PDL Data Transfer (Option)

Image data from PDLPCB is transferred to Page Memory. Coded data is transferred from System bus side.

There are following optional memory.

• DRAM Card (2,4,8 MB) for established page memory

Coding and decoding (MH/MR/MMR/JBIG  mode) is carried out by hardware codec device (SGCP).There are 2 codec as follows.

• SGCP MN86064 (IC60) : for image codec

Image bus is separated from I/O bus (System bus) by this codec. This codec codes from Image data to JBIG data when the date 
is transferred from Page Memory to Document Memory of System bus side.

• SGCP MN86064 (lC50) : for communication codec

This codec is used during TX/RX communication. Optional G3 PCB also has this codec device for communication.

• DMA function

     FRIP 

→

 Page Memory (DRAM)

:

Scanning route

     Page Memory (DRAM) 

→

 Image SGCP

:

Coding route

     Image SGCP 

→

 Page Memory (DRAM)

:

Decoding route

     Page Memory (DRAM) 

→

 IPC

:

Print route

25MHz

MOTOR

MEMORY CARD

OPTION

CCD

MN86075

(IC160)

SRAM

(IC170,171,172)

MASK
ROM

(IC141)

DZAC000167

PEC

(IC110)

DRAM

(IC120, 121)

SRAM

(IC131, 132)

MN86064

SGCP

Page Memory

Scanning Data

Print Data

40MHz

(IC130)

MOT
DRV

LED

STAMP

50MHz

32MHz

18.117MHz

5MHz

+5V Bus

Image
FROM

(System)

LPC

DRAM

2, 48MB

DZAC000209

(IC150)

Smoothing

Sub CPU

IPC

(IC140)

PDL

OPTION

BOARD

CNP4

CNP1

CNP

55

(IC171 for 

UF-885)

DZAC000168

22

This circuit consists of CCD unit, Scanning device FRIP5 and peripheral Op-Amp. Scanning analog signal (shading signal) which
produced by CCD PCB is amplified by OP-Amp. And it is converted from analog to degital and changed to binary signal (black and
white) by FRIP5.

1. Scanning LSI

FRIP5 has several functions as follows. Generating CCD drive clock, offset control, ABC control, Shading correction control,
MTF control, Reduction/magnification, Editing Half tone, Binary coding (black and white)

2. CCD Drive Control

OFCK1 and OFCK2 are generated by FRIP. OFSG,OFR1 and OFR2 are generated by IPC as based on FSG, FR1 and FCK1
from FRIP.
These clocks drive CCD unit and CCD unit generates shading signal.

3. Offset Control Circuit

Black level of Shading Signal is fixed to 0 V by Op -Amp (1C180). The offset level is decided by IC 180 pin 5 from FRIP before
scanning each document.

4. ABC Circuit (Auto Background Control)

This circuit adjusts ABC signal to most suitable level of contrast, even background of document is not same level as white
level.
A/D Converter in FRIP confirms the white level of shading signal from ABC Amp.(IC180). When the white level is too high,
FRIP decreases the voltage of FETD(pin 36), then reduce the shading signal Input level from ABC amp. 
And when the white level is too low, FRIP increases the voltage of FETD, then increases white level. White level of shading
signal for ABC amp is controlled to keep 3V through above control.

5. Shading Correction Circuit

This circuit consists of shading correction circuit in FRIP and shading SRAM (IC170/171). This circuit corrects distortion of
shading signal due to Scanning LED and optical lens. The circuit scans the reference white plate on the Transmission 
Document Guide before the document reaches the scanning point and writes the compensation value according to the 
distortion of the wave form into the SRAM (IC170/171). When the correction is carried out for each page during transmission
and copying.

6. System I/F of Scanning Data

Scanning signal which is converted to binary signal is transferred to Page Memory (IC120/121) by serial communication
between FRIP, IPC and PEC.

Scanning circuit can be checked by using Service Mode 5 (Scanning Data always out put)

SNS(DZEP000164)

MN86075(IC160)

MOTOR

CCD

ABC

SRAM

(IC170, 171, 172)

(IC171 for UF-885)

STK6712

(IC29)

LED

STAMP

DZAC000209

(IC150)

Sub CPU

FCB

APNT SENSOR

B4W SENSOR

BPNT SENSOR

SDOR SENSOR

Serial I/F

Main
CPU

APNT

BPNT

B4SN
SDOOR

IC10

API

IC60

Offset

OFR 1, 2, OFSG

CCD Drive Clock

CCD Drive Clock
OFSK0.1

A/D 

Converter

Shading

Correction

Reduction

Binary
Coding

IPC

PEC

PEC

DRAM

SRAM

VSDA

VSDAA

FRI, FCK1, FSG

SGCP

VSEN

VSCK

SENTIM

VREQ

VSENA

I/O Bus

23

1. Sub CPU

Sub CPU is a one chip CPU of 8 bit type to control scanning mechanism. It controls TX motor, Scanning LED, Verification
stamp and FRIP.

2. TX Motor Drive

Sub CPU controls Motor Driver (IC190) and drives TX motor.

This circuit consists of a recording picture control G/A IPC, Smoothing ROM (IC41) and its peripheral circuit.
IPC receives printed data from PEC as serial data and pass it to Laser Unit after following operation.

1. Smoothing Circuit

When receiving data (8dot/mm x 3.85,7.7,15.4line/mm) is converted to 16dot/mm x 15.4 line/mm resolution, current printed
data and 15 surround printed data are sent to Smoothing ROM through 16 bit line and the ROM sends smoothed dot data.
Due to this operation, distorted curved lines is smoothed.

2. Image Range Isolation Circuit

It identifies the halftone picture range and controls smoothing to eliminate blotching of the recording picture which has 
undergone error diffusion or other process.

3. Reduction Circuit

This circuit is used to process the received data so that it fits on the recording paper, according to the Fax Parameter settings
(70% - 100%).

4. Synchronization Control Circuit

Printed data is transferred from IPC to Laser Unit by three kind of timing clock. These are VSYNC for each page, HSYNC for
each line and dot clock. Dot clock is generated by X140 (for copy, RX) or X143 (for Printer & PDL I/F) connected to IPC. Due
to the resolution of printed data, IPC controls the resolution of printer as follows.

5. Laser Pulse Width Control

After smoothing, IPC controls laser pulse width by software setting for print quality.

16 dot/mm x 15.4 line/mm

:

copy & G3 receiving data

600 dpi x 600 dpi

:

Printer Interface & PDL Interface

24

IPC controls LBP CPU on LPC PCB.

1. Command / Status Interface

LBP CPU sends back printer condition (Status) due to request of IPC (Command).

PCB

FCB

FAX BLOCK

IC18

SMOOTHING

MASKROM

IC1, 17

PAGE MEMORY

DRAM

IPC

Laser 

UNIT

LPC  PCB

IC51

Single

CHIP

CPU

LBP CPU

LBP

Mech

Control 

PRINT DATA I/F

Print Data 

(

VDO

)

PRINTER READY (PRDY)

PRINT REQUEST (PRINT)

HORIZONTAL SYNCHRONOUS (HSYNC)

PRINTER CONDITION I/F

COMMAND/STATUS I/F

COMMAND DATA BUSY (CBSY)

COMMAND DATA (CMD)

SERIAL CLOCK (LPSCLK)

STATUS DATA BUSY (SBSY)

STATUS DATA (STA)

ROM

 RAM 

Laser  I/F

VERTICAL SYNCHRONOUS (VSYNC)

(Every Line)

(Every Page)

Laser Pulse

Width Control

Reduction

PEC

S/P

Reduction

S/P

Serial I/F

nPRDY

(Controller        Printer)

nVSYNC

(Controller        Printer)

nHSYNC

(Controller        Printer)

nPRNT

(Controller        Printer)

nVDO

(Controller        Printer)

2mS

(1 Raster)

1 Raster  Video data

1 Page Print

nPRDY

Printer Ready

nPRNT

Print

nVSYNC

Top of Page

nHSYNC

Horizontal Synchronous

nVDO

Video Signal