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17

Main Motor ON

IC51, Pin6

Main Motor

Rotation defect

FCB Initial End

Hard Reset

Start Watching I/O Port

IC51

Pin48

STOP

Door Open

2nd JAM Cover Open

IC51

Pin26

Fuser Heat-up

(Lamp ON)

IC51, Pin34

IC51 Pin47

Vin < 0.04V

IC51 Pin47

Vin increase
under 0.04V

Thermistor Open

Abnormal temparature

IC51

Pin5

IC51

Pin38

IC51

Pin37

Regist Motor ON

Exit Sensor ON

Service

Error

B

STOP

Service

Error

Service

Error

STOP

STOP

STOP

STOP

STOP

L

L

H

Y

Y

L

L

H

H

N

N

L

H

H

H : Heater OFF

L : Heater ON

(Watching during Initial Operation)

18

Fan not Ready

IC51

Pin4

Internal Process of
High Voltage IC51,

Pin 15, 16, 17, 18, 19

Service

Error

H

B

Fan Motor ON

IC51, Pin11

IC51 Pin49

Vin < 1.4V

Fuser Idle

(Lamp OFF)

Stand-by

Motor OFF

No Cartrige

STOP

Y

Stand-by : Printer Ready

STOP

: Printer not Ready

L : STOP

H : High Speed

L

N

19

System Control Block consists of following IC and it controls general function FAX.

1. System CPU : 32-bit RISC (Reduced Instruction Set Computer) type CPU

This CPU is integrated CPU and following device.

2. System Control Gate Array (MSC)

• Mask ROM

:

Boot program (64kb)

• DMA Control

:

G3 CODEC (SGCP) 

←→

 Document Memory (FROM)

• Interrupt Control

:

Several Mechanism timing and Modem data transfer control

• DRAM Control

:

RAS & CAS and Refresh control during power on

• I/O Port

:

I/O device master reset, LCU/LCE PCB control and etc.

• Panel I/F 

:

Serial Communication (Command/Status) with Panel Unit

• Sub CPU I/F

:

Serial Communication (Command/Status) with Sub CPU for Scanning

• DMA Control

:

Image CODEC (SGCP) 

←→

 Document Memory (FROM)

:

Optional Printer I/F 

←→

 Document Memory (FROM)

• Interrupt Control

:

Receipt & transfer to CPU for interrupt from Modem, FRIP,IPC, etc

• DRAM Control

:

Address signal and RAS/CAS generation for DRAM

• Address Decoder

:

Chip select signal generate from address signal

• Bus Control

:

Data control between System bus (+3.3V) and I/O bus (+5V)

(+5V Bus)

(+3V Bus)

MEMORY CARD

OPTION

Program

FROM

(IC43)

Main CPU

SH7041

(IC10)

DRAM

(IC4,5)

FRAM

1/2/4/8MB

FROM

(IC41)

7.1MHz

1.25MHz

DZAC000166/MSC

(IC20)

Sub CPU

uPD78058

(IC150)

API

DZZSP58025

(IC60)

SGCP

MN86064

(IC50)

MN195004

(IC80)

G3B

Image Block

FRIP, SGCP
IPC, PEC

OPTION

BOARD

PDL

OPTION

BOARD

FROM
(IC82)

TR88017

(IC90)

SRAM

CODEC for Communicatin

(IC81)

PRT

OPTION

BOARD

Panel Block

Scanning
Mechanism
Control

Document Memory
Backup Data

Document Memory

Work Memory
ECM Buffer Memory

Modem Program

Modem CPU

Analog Modem

20

3. Other Peripheral Device

• Image Data Control

:

FRIP5 (Scanning), IPC (Image data editing), PEC (Image data transfer), Image 
SGCP (Codec for image data)

• Communication Control

:

Modem CPU, API (I/O Port), G3 SGCP (Codec for communication)

• FROM (IC43)

:

System control program (2MB)

• FROM (IC42)

:

Document memory, Job management info., Real time clock, RAM setting, 
Journal, Telephone No., TX/RX/Print counter (UF-895:2MB, UF-885:1MB)

• DRAM (IC30)

:

CPU work memory, line memory, ECM buffer

• System Reset

:

Reset IC (IC21) always watches 5V (pin3). When watching Voltage becomes to 
less than 4.5V, system reset signal (pin2) becomes to 0V.  Reset interval is 
130ms.

• Watch Dog Timer

:

Timer: When software runaway, CPU puts out reset signal (interval is 2.0

µ

s) to 

MSC and system reset is carried out.

CPU

Reset

IC

PNL

CPU

SUB
CPU

LPC

OP

PC or P

OP

232C

MSC

DRAM

FROM

SGCP

3

5

PEC

IPC

API

FRIP

OP

G3

PDL

OP

SGCP

Modem

FROM

Card

: 3V Signal

: 3VIC

3V

5V

MSC

nIORST3V

FROMRST

nOP1RST

nIORST

nWDTOVF

nMDRST

nRST3V

CPU

MSC

24

MHz

SUB
CPU

40

MHz

50

MHz

32

MHz

18.117

MHz

DRAM

FROM

SGCP

PEC

IPC

API

FRIP

OP

PDL

OP

G3

SGCP

Modem

FROM

Card

: 3V Signal

: 3VIC

SUBCLK (4.166 MHz)

CK14M (14.2 MHz)

CK14MLV

nCK7MLV

7.1 MHz  Crystal

FRMCLK (25 MHz)

PEC

Clock

Modem

Clock

Scanning

Clock

Print

Clock

Print (600 dpi)

Clock

3V

5V