Panasonic UF-885 / UF-895 Service Manual / Other ▷ View online
49
3.1.7
MODEM (MN195004)
3.1.8
GCP (MN86064A)
Pin No.
Pin Name
Type
Description
108-111
114-128
114-128
MAD18-0
O
Address Bus (Modem Internal)
103-107
MAD23-19
O
Address Bus (Modem Internal)
1-8
MD7-0
I/O
Data Bus (Modem Internal)
99
UC0
O
FROM Chip Select
100
UC1
O
Not Used
101
MCS3
O
V34ASIC Chip Select
102
UC3
O
Not Used
9
SYSA
O
-
10
CXSL
I
Clock Select
11
CX
I
Modem Clock
12
RSMD
I
Modem Reset
15
MWT
O
Write Enable
16
MRD
O
Read Enable
17
MRNW
O
Read and Write Strove
18
BA
O
Not used
19
HALT
I
Bus Halt Request
20
EQMD
O
(Eye Pattern Data)
21
ADCK
I
(Eye Pattern Clock)
22
EYSY
O
(Synchronous Signal of Eye Pattern Data)
23
PLSD
O
RX Signal Gain Control
24
MOI
I
Monitor Interrupt
25
FIFP
O
Not used
26,27
CLKT1,2
I
for Test
28
EXCLA
I
for Test
29
ACS
O
Analog Chip Select
30
INVD
O
Filter Select
31
HLSEL
O
Filter Select
32
NCHSEL
O
Filter Select
33
EXCLB
I
for Test
34-41
-
-
Not used
42-45
MOD0-3
I
Mode Select
46-61
S0-15
-
I/O Port
62-66
-
-
Not used
67
SPCK
I
External Interrupt
68
BRCK
I
External Interrupt
69
NMI
I
DTE Interrupt
70
-
I
-
71
-
I
-
72-75
-
-
SIO
78-93
-
-
Motor Control (Not used)
94
-
O
Video I/F (Not used)
95
-
I
Video I/F (Not used)
96
-
I
Video I/F (Not used)
97
-
O
Video I/F (Not used)
98
-
I
Video I/F (Not used)
13,77,113
-
Power Supply
14,76,112
-
GND Potential
Pin No.
Pin Name
Type
Description
35
A3
I
Address input pins. Used for addressing internal registers.
36
A2
I
Address input pins. Used for addressing internal registers.
37
A1
I
Address input pins. Used for addressing internal registers.
38
A0
I
Address input pins. Used for addressing internal registers.
9
D15
I/O
Data input/output pins. Used to transfer data to and from system bus.
10
D14
I/O
Data input/output pins. Used to transfer data to and from system bus.
11
D13
I/O
Data input/output pins. Used to transfer data to and from system bus.
12
D12
I/O
Data input/output pins. Used to transfer data to and from system bus.
13
D11
I/O
Data input/output pins. Used to transfer data to and from system bus.
14
D10
I/O
Data input/output pins. Used to transfer data to and from system bus.
15
D9
I/O
Data input/output pins. Used to transfer data to and from system bus.
16
D8
I/O
Data input/output pins. Used to transfer data to and from system bus.
17
D7
I/O
Data input/output pins. Used to transfer data to and from system bus.
18
D6
I/O
Data input/output pins. Used to transfer data to and from system bus.
19
D5
I/O
Data input/output pins. Used to transfer data to and from system bus.
20
D4
I/O
Data input/output pins. Used to transfer data to and from system bus.
50
21
D3
I/O
Data input/output pins. Used to transfer data to and from system bus.
22
D2
I/O
Data input/output pins. Used to transfer data to and from system bus.
23
D1
I/O
Data input/output pins. Used to transfer data to and from system bus.
24
D0
I/O
Data input/output pins. Used to transfer data to and from system bus.
26
*UBE
I
Upper byte enable. Indicates D15-8 data is valid.
6
*RD
I
Read enable input pin. Indicates to read data from register.
7
*WR
I
Write enable input pin. Indicates to write data to register.
25
*CS
I
Chip select signal input pin. Indicates to access register.
1
*HEX
I
Select Data bus width. Selects bit width of data bus for system bus. (0:16 bit,
1:8 bit)
1:8 bit)
100
*RESET
I
Reset.
2
INTR0
O
Interrupt Request 0.
3
INTR1
O
Interrupt Request 1.
4
INTR2
O
Interrupt Request 2.
27
REQC0
O
DMA transfer output request 0. Indicates request from channel 0 to output data
through DMA transfer.
through DMA transfer.
28
REQC1
O
DMA transfer output request 1. Indicates request from channel 0 to output data
through DMA transfer.
through DMA transfer.
29
REQD0
O
DMA transfer input request 0. Indicates request from channel 0 to output data
through DMA transfer.
through DMA transfer.
30
REQD1
O
DMA transfer input request 1. Indicates request from channel 1 to output data
through DMA transfer.
through DMA transfer.
31
*ACKC0
I
DMA transfer output reply 0. Indicates that request of DMA transfer from REQC0 is
admitted and is output data through DMA transfer.
admitted and is output data through DMA transfer.
32
*ACKC1
I
DMA transfer output reply 1. Indicates that request of DMA transfer from REQC1 is
admitted and is output data through DMA transfer.
admitted and is output data through DMA transfer.
33
*ACKD0
I
DMA transfer input reply 0. Indicates that request of DMA transfer from REQC0 is
admitted and is input data through DMA transfer.
admitted and is input data through DMA transfer.
34
*ACKD1
I
DMA transfer input reply 1. Indicates that request of DMA transfer from REQC1 is
admitted and is input data through DMA transfer.
admitted and is input data through DMA transfer.
5
CLKIN
I
System clock input pin.
8
CLKOUT
O
System clock output pin. Half frequency of CLKIN clock is output to outside.
60
IA15
O
Image address output pin.
61
IA14
O
Image address output pins. Generates address that is accessed on image bus.
62
IA13
O
Image address output pins. Generates address that is accessed on image bus.
63
IA12
O
Image address output pins. Generates address that is accessed on image bus.
64
IA11
O
Image address output pins. Generates address that is accessed on image bus.
65
IA10
O
Image address output pins. Generates address that is accessed on image bus.
66
IA9
O
Image address output pins. Generates address that is accessed on image bus.
67
IA8
O
Image address output pins. Generates address that is accessed on image bus.
68
IA7
O
Image address output pins. Generates address that is accessed on image bus.
69
IA6
O
Image address output pins. Generates address that is accessed on image bus.
70
IA5
O
Image address output pins. Generates address that is accessed on image bus.
71
IA4
O
Image address output pins. Generates address that is accessed on image bus.
72
IA3
O
Image address output pins. Generates address that is accessed on image bus.
73
IA2
O
Image address output pins. Generates address that is accessed on image bus.
74
IA1
O
Image address output pins. Generates address that is accessed on image bus.
75
IA0
O
Image address output pins. Generates address that is accessed on image bus.
78
ID15
I/O
Image data input/output pins. Used to transfer data to and from image bus.
79
ID14
I/O
Image data input/output pins. Used to transfer data to and from image bus.
80
ID13
I/O
Image data input/output pins. Used to transfer data to and from image bus.
81
ID12
I/O
Image data input/output pins. Used to transfer data to and from image bus.
82
ID11
I/O
Image data input/output pins. Used to transfer data to and from image bus.
83
ID10
I/O
Image data input/output pins. Used to transfer data to and from image bus.
84
ID9
I/O
Image data input/output pins. Used to transfer data to and from image bus.
85
ID8
I/O
Image data input/output pins. Used to transfer data to and from image bus.
86
ID7
I/O
Image data input/output pins. Used to transfer data to and from image bus.
87
ID6
I/O
Image data input/output pins. Used to transfer data to and from image bus.
88
ID5
I/O
Image data input/output pins. Used to transfer data to and from image bus.
89
ID4
I/O
Image data input/output pins. Used to transfer data to and from image bus.
90
ID3
I/O
Image data input/output pins. Used to transfer data to and from image bus.
91
ID2
I/O
Image data input/output pins. Used to transfer data to and from image bus.
92
ID1
I/O
Image data input/output pins. Used to transfer data to and from image bus.
93
ID0
I/O
Image data input/output pins. Used to transfer data to and from image bus.
41
IHREQ
O
Image bus request output pin. Indicates request of possession from image bus.
42
IHACK
I
Image bus input reply pin. Indicates that the possession of image bus is given.
49
IREADY
I
Image data reply pin. Indicates that read/write of data is completed.
52
*IMUE
O
Memory upper byte valid output pin. Indicates to access memory on ID15-8.
53
*IMLE
O
Memory lower byte valid output pin. Indicates to access memory on ID7-0.
45
*IMR
O
Image memory read output pin. Indicates to read memory on image bus.
47
*IMW
O
Image memory write output pin. Indicates to write memory on image bus.
55
EXA0/*DSTR0
O
Image bus address extension bit 0. DMA transfer start 0. Indicates DMA transfer
to be performed from I/O device to memory.
to be performed from I/O device to memory.
54
EXA1/*DSTR1
O
Image bus address extension bit 0. DMA transfer start 1. Indicates DMA transfer
to be performed from memory to I/O device.
to be performed from memory to I/O device.
Pin No.
Pin Name
Type
Description
51
3.1.9
DPRAM (Dual Port RAM)
44
DREQ0
I
DMA transfer request 0. Indicates request of DMA transfer from I/O device to mem-
ory.
ory.
43
DREQ1
I
DMA transfer request 1. Indicates request of DMA transfer from memory to I/O
device.
device.
56
*DACK0
O
DMA transfer reply 0. Indicates to reply to DREQ0 and perform DMA transfer from
I/O device to memory.
I/O device to memory.
57
*DACK1
O
DMA transfer reply 1. Indicates to reply to DREQ1 and perform DMA transfer from
memory to I/O device.
memory to I/O device.
51
*DCMP0
O
DMA transfer completion 0. Indicates DMA transfer for 1 line from I/O device to
memory has completed properly.
memory has completed properly.
50
*DCMP1
O
DMA transfer completion 1. Indicates DMA transfer for 1 line from memory to I/O
device has completed properly.
device has completed properly.
46
*IOR
O
I/O device read output pin. Indicates to read I/O device on image bus.
48
*IOW
O
I/O device write output pin. Indicates to write I/O device on image bus.
96
TEST3
I
Test mode. Connects all pins to GND.
97
TEST2
I
Test mode. Connects all pins to GND.
98
TEST1
I
Test mode. Connects all pins to GND.
99
TEST0
I
Test mode. Connects all pins to GND.
40
VDD1
I
+5V. Connects all pins to +5V.
59
VDD2
I
+5V. Connects all pins to +5V.
77
VDD3
I
+5V. Connects all pins to +5V.
95
VDD4
I
+5V. Connects all pins to +5V.
39
VSS1
I
GND. Connects all pins to GND.
58
VSS2
I
GND. Connects all pins to GND.
76
VSS3
I
GND. Connects all pins to GND.
94
VSS4
I
GND. Connects all pins to GND.
Pin No.
Pin Name
Type
Description
85,40
CEL, CER
I
Chip Enable
87,37
R/WL, R/WR
I
Read/Write Enable
89,36
OEL, OER
I
Output Enable
44-50, 55-59,
66-71, 76-81
A0L-A11/12L,
A0R-A11/12R
I
Address
3-8,10,11,
14-16,18-23,
26-33,35,90,91,
93-100
I/O0L-I/O15/
17L, I/O0R-
I/O15/17R
I/O
Data Bus input/output
86,39
SEML, SEMR
I
Semaphore Enable
84,41
UBL, UBR
I
Upper Byte Select
83,42
LBL, LBR
I
Lower Byte Select
65,60
INTL, INTR
O
Interrupt Flag
64,61
BUSYL, BUSYR
I/O
Busy Flag
62
M/S
I
Master or Slave Select
12,17,88
VCC
-
Power
9,13,34,38,63,92
GND
-
Ground
Pin No.
Pin Name
Type
Description
52
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