DOWNLOAD Panasonic WV-CU950 Service Manual ↓ Size: 4.41 MB | Pages: 59 in PDF or view online for FREE

Model
WV-CU950
Pages
59
Size
4.41 MB
Type
PDF
Document
Service Manual
Brand
Device
Video Monitoring / SYSTEM CONTROLLER
File
wv-cu950.pdf
Date
PREV: Panasonic WV-CU850 Service Manual

Panasonic WV-CU950 Service Manual ▷ View online

<LOCATION MARK>
SDRAM
FLASH ROM
HD300ROM (CN)
ADDR[25-0]
nWE[3]
nWE[2]
nWE[0]
nWE[1]
DATA[31-0]
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
ADDR[16]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[12]
ADDR[14]
ADDR[14]
ADDR[11]
ADDR[10]
ADDR[9]
ADDR[8]
ADDR[7]
ADDR[6]
ADDR[13]
ADDR[2]
ADDR[3]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
ADDR[8]
ADDR[18]
ADDR[19]
ADDR[21]
ADDR[20]
ADDR[9]
ADDR[10]
ADDR[11]
ADDR[12]
ADDR[13]
ADDR[14]
ADDR[15]
ADDR[16]
ADDR[1]
ADDR[17]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
DATA[12]
DATA[13]
DATA[14]
DATA[15]
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
nWE[1]
nWE[0]
ADDR[15]
nCS[3]
nWE[3-0]
nCS[0]
nCS[2]
nCS[3]
nCS[4]
nCS[5]
nCS[6]
ADDR[25]
ADDR[24]
ADDR[25]
ADDR[24]
nCS[6]
nCS[5]
nCS[0]
nCS[2]
nCS[3]
nCS[4]
nCS[0]
nCS[2]
nCS[3]
nCS[4]
nCS[5]
nCS[6]
nBS
nWE[3]
nWE[2]
nWE[1]
nWE[0]
nRAS3
nRAS3
nCAS
nCAS
RD/nWR
RD/nWR
nRD
nCS[0,2,3,4,5,6]
ADDR[22]
CKE
DGND
10k
Z29
1
2
3
6
4
5
7
8
R96
0
nFLASH_ACC
R86
22
ADDR[25-0]
TD59
nFLASH_BUSY
C55
33/6.3
C79
33/10
R82
22
R81
22
nWE[3-0]
R88
22
TD63
R78
4.7k
R19
100k
R14
100k
nRD
IC13
1
VDD_1
2
DQ0
3
VDDQ_1
4
DQ1
5
DQ2
6
VSSQ_1
7
DQ3
8
DQ4
9
VDDQ_2
10
DQ5
11
DQ6
12
VSSQ_2
13
DQ7
14
VDD_2
15
LDQM
16
WE
17
CAS
18
RAS
19
CS
20
BA0
21
BA1
22
A10/AP
23
A0
24
A1
25
A2
26
A3
27
VDD_3
28
VSS_1
29
A4
30
A5
31
A6
32
A7
33
A8
34
A9
35
A11
36
NC_1
37
CKE
38
CLK
39
UDQM
40
NC_2
41
VSS_2
42
DQ8
43
VDDQ_3
44
DQ9
45
DQ10
46
VSSQ_3
47
DQ11
48
DQ12
49
VDDQ_4
50
DQ13
51
DQ14
52
VSSQ_4
53
DQ15
54
VSS_3
C78
0.1
R85
22
C61
0.1
C179 0.1
DGND
R90
22
L30
8.2
TD57
nFLASH_CS
C68
0.1
nFLASH_WE
R228
10k
4.7k
4.7k
nBS
RD/nWR
L29
8.2
R108
330
DGND
C60
0.1
Z28
1
2
3
6
7
8
3R3V
R92
22
1R9V
R113
4.7k
TD61
C59
0.1
TD51
R79
4.7k
L31
8.2
R89
22
R87
22
R97
0
R95
4.7k
TD62
R91
22
R99
OPEN
TD52
TD58
R93
4.7k
nFLASH_OE
L33
8.2
R98
OPEN
C75
0.1
R80
22
nPROM_CS
Z19
4.7k
1
2
3
6
4
5
7
8
3R3V
nRESETP
C67
0.1
TD50
C74
0.1
R104
OPEN
R110 OPEN
R227
4.7k
TD49
R94
4.7k
R77
22
nCS[0,2,3,4,5,6]
R84
22
R109 470
C66
0.1
TD60
3R3V
Z27
1
2
3
6
4
5
4
5
7
8
R83
22
C73 33/10
L28
8.2
C65
0.1
DATA[31-0]
C58
33/10
91
VSS 2
92
A24
93
VCC_2
94
A25
95
BS/PTK[4]
96
RD
97
WE0/DQMLL
98
WE1/DQMLU/WE
99
WE2/DQMUL/ICIORD/PTK[6]
100
VssQ_8
101
WE3/DQMUU/ICIOWR/PTK[7]
102
VccQ_8
103
RD/WR
104
PTE[7]/PCC0RDY/AUDSYNC
105
CS0
106
CS2
107
CS3
108
CS4/PTK[2]
109
CS5/CE1A/PTK[3]
110
CS6/CE1B
111
CE2A/PTE[4]
112
CE2B/PTE[5]
113
AFE_HC1/USB1d_DPLS/PTK[0]
114
AFE_RLYCNT/USB1d_DMNS/PTK[1]
115
VssQ_9
116
AFE_SCLK/USB1d_TXDPLS
117
VccQ_9
118
119
120
121
PTM[4]/PINT[4]/AFE_RDET/
USB1d_TxDMNS
122
RESERVED/USB1d_SUSPEND
123
USB1_ovr_crnt/USBF_VBUS
124
USB2__ovr_crnt
125
RTS2/USB1d_TXENL
126
PTE[2]/USB1_pwr_en
127
PTE[1]/USB2_pwr_en
128
CKE/PTK[5]
IC15
1
A15
2
A14
3
A13
4
A12
5
A11
6
A10
7
A9
8
A8
9
A19
10
A20
11
WE
12
RESET
13
N.C.
14
WP/ACC
15
RY/BY
16
A18
17
A17
18
A7
19
A6
20
A5
21
A4
22
A3
23
A2
24
A1
25
A0
26
CE
27
VSS_1
28
OE
29
DQ0
30
DQ8
31
DQ1
32
DQ9
33
DQ2
34
DQ10
35
DQ3
36
DQ11
37
VCC
38
DQ4
39
DQ12
40
DQ5
41
DQ13
42
DQ6
43
DQ14
44
DQ7
45
DQ15/A-1
46
VSS_2
47
BYTE
48
A16
Z20
33
1
2
3
6
7
8
4
5
ETHER
BOARD
(1/3)
<INDEX>
IC1
D1
IC2
C1,C2
IC3
E1,E2,
F1,F2
IC5
D1,D2
IC7
D2
IC8
C2
IC9
E3
IC10
A3
IC11
A3
IC12
B3,B4,B5,
C3,C4,C5,
D3,D4,D5
IC13
C7,D7
IC14
B7,C7
IC15
C8,D8
Q1
E1,E2
Q2
E1,E2
D1
E1
D2
E1
4-2-3
SCHEMATIC DIAGRAM OF ETHER BOARD (1/3) [
2
]
4-2-4
SCHEMATIC DIAGRAM OF ETHER BOARD (1/3) [
3
]
<LOCATION MARK>
TO
MAIN
BOARD
CN6
NMI
RTC_CLK
CPU
DATA[3]
DATA[2]
DATA[0]
IRQ[4]
IRQ[3]
IRQ[2]
IRQ[1]
IRQ[5-0]
IRQ[0]
DATA[1]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[16]
DATA[17]
DATA[18]
DATA[19]
DATA[20]
DATA[21]
DATA[22]
DATA[23]
DATA[31]
DATA[30]
DATA[29]
DATA[28]
DATA[27]
DATA[26]
DATA[25]
DATA[24]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
DATA[6]
DATA[5]
DATA[4]
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
DATA[12]
DATA[13]
DATA[14]
DATA[15]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[20]
DATA[21]
DATA[22]
DATA[23]
DATA[24]
DATA[25]
DATA[26]
DATA[27]
DATA[28]
DATA[29]
DATA[30]
DATA[31]
IRQ[0]
IRQ[1]
IRQ[2]
IRQ[3]
IRQ[5]
IRQ[4]
UC_TX
1.9V_CPU
3.3V_CPU
SW2
1
2
3
4
5
5
GND
6
GND
7
TX
8
RX
9
SGND
10
RST
11
GX_STATUS
12
GXCOM_Enable
Attachment1
Attachment2
R31
10k
C47
0.1
IC2
1
1OE
2
1A
3
1Y
4
2OE
5
2A
6
2Y
7
GND
8
3Y
9
3A
10
3OE
11
4Y
12
4A
13
4OE
14
VCC
R18
OPEN
TD24
R4
0
C39
12p
C5 OPEN
R5
0
R28
10k
CN2
OPEN
OPEN
1
VBUS
2
D-
3
D+
4
GND
Attachment1
Attachment2
Attachment3
Attachment4
DGND
R61
0
C52
0.1
Z1
10k
1
2
36
45
7
8
D35
OPEN
Z2
1
2
36
45
7
8
R69
10k
C9
0.1
R13
OPEN
D32
OPEN
D28
OPEN
DGND
DGND
VS1
OPEN
Z6
1
2
36
7
8
IC4
OPEN
1
ENA
2
FLAG_A
3
FLAG_B
4
ENB
5
OUT_B
6
GND
7
IN
8
ONT_A
R20
OPEN
DGND
R43
10k
C21
OPEN
C3 OPEN
R32
OPEN
C15 OPEN
R30
10k
DGND
R15
1M
C7
OPEN
R23
OPEN
TD21
C14
OPEN
C8
OPEN
R16
OPEN
DGND
D34
OPEN
Z12
1
2
36
7
8
C54
100p
R7 OPEN
DGND
R51 10k
Z18
1
2
36
7
8
C35
0.1
C4 OPEN
3R3V
R35
OPEN
R2
22
DGND
C34
0.1
R65
4.7k
4.7k
4.7k
C1 OPEN
TD25
C50
0.1
VS2
OPEN
BOOTSEL0
R223
10k
C36
0.1
R38
10k
TD23
R67
C23
OPEN
L3
OPEN
nRESETP
IRQ[5-0]
R17
OPEN
CN3
1
VBUS
2
D-
3
D+
4
GND
Attachment1
Attachment2
Attachment3
R27
OPEN
SW1
1
2
3
4
5
6
7
8
R29
10k
L5
OPEN
1
3
4
2
DGND
DGND
5V
C22
OPEN
X2
1
2
4
3
C27
0.1
C10
OPEN
R26
OPEN
R34
OPEN
Z4
10k
10k
10k
10k
10k
10k
10k
10k
1
2
36
7
8
3.3V_CPU
R3
0
TD22
DGND
L2
OPEN
R1
22
L9
OPEN
1
3
4
2
Z10
1
2
36
7
8
R24
OPEN
C49
100p
V5DRS
DGND
Z8
1
2
36
7
8
D30
OPEN
C26
0.1
D33
OPEN
IC10
1
R54
10k
TD20
R52
4.7k
D29
OPEN
L4
OPEN
R25
OPEN
L1
OPEN
IC11
(1/7)
(1/7)
1
2
2
(32.768KHz)
L7
OPEN
DGND
Z16
1
2
36
7
8
C2 OPEN
R6 OPEN
C28
33/10
D31
OPEN
C178
0.1
C41
12p
BOOTSEL1
R39
1k
DGND
L14
8.2
C24
OPEN
IC8
1
1A
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
GND
8
3Y
9
3A
10
3B
11
4Y
12
4A
13
4B
14
VCC
C37
0.1
R42 10k
R33
OPEN
DGND
Z14
1
2
36
7
8
DGND
R44
4.7k
IC12
1
Vcc_RTC
2
XTAL2
3
EXTAL2
4
Vss_RTC
5
MD1
6
MD2
7
NMI
8
IRQ0/IRL0/PTH[0]
9
IRQ1/IRL1/PTH[1]
10
IRQ2/IRL2/PTH[2]
11
IRQ3/IRL3/PTH[3]
12
IRQ4#/PTH[4]
13
VEPWC
14
VCPWC
15
MD5
16
BREQ
17
BACK
18
VssQ_1
19
CKIO2
20
VccQ_1
21
D31/PTB[7]
22
D30/PTB[6]
23
D29/PTB[5]
24
D28/PTB[4]
25
D27/PTB[3]
26
D26/PTB[2]
27
D25/PTB[1]
28
D24/PTB[0]
29
VssQ_2
30
D23/PTA[7]
31
VccQ_2
32
D22/PTA[6]
33
D21/PTA[5]
34
D20/PTA[4]
35
VSS_1
36
D19/PTA[3]
37
VCC_1
38
D18/PTA[2]
39
D17/PTA[1]
40
D16/PTA[0]
41
D15
42
VssQ_3
43
D14
44
VccQ_3
45
D13
46
D12
47
D11
48
D10
49
D9
50
D8
51
D7
52
D6
53
VssQ_4
54
D5
55
VccQ_4
56
D4
57
D3
58
D2
59
D1
60
D0
205
LCD10/PTC[6]/PINT[2]
206
LCD9/PTC[5]/PINT[1]
207
VssQ_13
208
LCD8/PTC[4]/PINT[0]
209
VccQ_13
210
LCD7/PTD[3]
211
LCD6/PTD[2]
212
LCD5/PTC[3]
213
LCD4/PTC[2]
214
LCD3/PTC[1]
215
LCD2/PTC[0]
216
LCD1/PTD[1]
217
LCD0/PTD[0]
218
DREQ0/PTD[4]
219
LCLK/UCLK/PTD[6]
220
RESETP
221
CA
222
MD3
223
MD4
224
Scan_testen
225
AVCC_USB_1
226
USB1_P[analog]
227
USB1_M[analog]
228
AVSS_USB
229
USB2_P[analog]
230
USB2_M[analog]
231
AVCC_USB_2
232
AVSS_1
233
AN[2]/PTL[2]
234
AN[3]/PTL[3]
235
AN[4]/PTL[4]
236
AN[5]/PTL[5]
237
AVCC
238
AN[6]/PTL[6]/DA[1]
239
AN[7]/PTL[7]/DA[0]
240
AVSS_2
Z3
33
33
33
33
33
33
33
33
1
2
36
7
8
Z5
1
2
36
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
7
8
Z7
1
2
36
7
8
Z9
1
2
36
7
8
Z11
1
2
36
7
8
Z13
1
2
36
7
8
Z15
1
2
36
7
8
Z17
1
2
36
7
8
1
A
B
C
2
3
4
5
4-2-5
SCHEMATIC DIAGRAM OF ETHER BOARD (1/3) [
4
]
<LOCATION MARK>
HD300ROM (CN)
DATA[3]
DATA[2]
DATA[0]
DATA[23]
DATA[22]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[31]
DATA[30]
DATA[29]
DATA[28]
DATA[27]
DATA[26]
DATA[25]
DATA[24]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[12]
ADDR[15]
ADDR[7]
ADDR[8]
ADDR[9]
ADDR[10]
ADDR[11]
ADDR[13]
ADDR[14]
ADDR[16]
DATA[21]
nWE[3]
nWE[2]
ADDR[14]
ADDR[16]
nCS[3]
ADDR[6]
DATA[1]
DATA[4]
DATA[5]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
DATA[5]
DATA[4]
ADDR[25]
ADDR[24]
ADDR[23]
ADDR[22]
ADDR[21]
ADDR[20]
ADDR[19]
ADDR[18]
ADDR[17]
ADDR[16]
ADDR[15]
ADDR[14]
ADDR[13]
ADDR[12]
ADDR[11]
ADDR[10]
ADDR[9]
ADDR[8]
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
ADDR[25]
ADDR[24]
ADDR[23]
ADDR[22]
ADDR[21]
ADDR[20]
ADDR[19]
ADDR[18]
ADDR[17]
ADDR[16]
ADDR[15]
ADDR[14]
ADDR[13]
ADDR[12]
ADDR[11]
ADDR[10]
ADDR[9]
ADDR[8]
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
nBS
nRAS3
nCAS
RD/nWR
ADDR[9]
ADDR[8]
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[19]
ADDR[20]
ADDR[18]
ADDR[10]
ADDR[11]
ADDR[12]
ADDR[13]
ADDR[14]
ADDR[15]
ADDR[16]
ADDR[1]
DATA[31-0]
DATA[15]
DATA[0]
DATA[7]
DATA[8]
DATA[14]
DATA[1]
DATA[6]
DATA[9]
DATA[13]
DATA[2]
DATA[5]
DATA[10]
DATA[12]
DATA[3]
DATA[4]
DATA[11]
nRD
nRD
nPROM_CS
ADDR[17]
ADDR[21]
10k
10k
10k
10k
10k
10k
10k
Z29
1
2
3
6
4
5
4
5
4
5
4
4
5
5
4
5
4
5
7
8
Z30
1
2
3
6
7
8
Z35
1
2
3
6
7
8
C70
0.1
IC14
1
VDD_1
2
DQ0
3
VDDQ_1
4
DQ1
5
DQ2
6
VSSQ_1
7
DQ3
8
DQ4
9
VDDQ_2
10
DQ5
11
DQ6
12
VSSQ_2
13
DQ7
14
VDD_2
15
LDQM
16
WE
17
CAS
18
RAS
19
CS
20
BA0
21
BA1
22
A10/AP
23
A0
24
A1
25
A2
26
A3
27
VDD_3
28
VSS_1
29
A4
30
A5
31
A6
32
A7
33
A8
34
A9
35
A11
36
NC_1
37
CKE
38
CLK
39
UDQM
40
NC_2
41
VSS_2
42
DQ8
43
VDDQ_3
44
DQ9
45
DQ10
46
VSSQ_3
47
DQ11
48
DQ12
49
VDDQ_4
50
DQ13
51
DQ14
52
VSSQ_4
53
DQ15
54
VSS_3
R9
10k
CN8
1
A18
2
A19
3
A17
4
A8
5
A7
6
A9
7
A6
8
A10
9
A5
10
A11
11
A4
12
A12
13
A3
14
A13
15
A2
16
A14
17
A1
18
A15
19
A0
20
A16
21
CS
22
A20/BYTE#
23
GND
24
GND
25
OE
26
D15
27
D0
28
D7
29
D8
30
D14
31
D1
32
D6
33
D9
34
D13
35
D2
36
D5
37
D10
38
D12
39
D3
40
D4
41
D11
42
VCC
43
VCC
44
GND
45
GND
46
GND
47
GND
48
GND
49
GND
50
GND
Attachment1
Attachment2
3R3V
R105
OPEN
Z33
1
2
3
6
7
8
C56
33/10
33/10
C71
0.1
R111
22
A3
27
VDD_3
28
VSS_1
A4
C61
0.1
R101
0
C54
100p
C64
0.1
DGND
Z18
1
2
36
7
8
C69
0.1
DGND
C68
0.1
DGND
DGND
C76
0.1
C62
0.1
C63
100p
C72
0.1
R92
22
C57
R106
330
DGND
R91
22
R99
OPEN
R102
OPEN
C17
0.1
10k
R98
OPEN
Z32
1
2
3
6
7
8
R112
OPEN
C77
0.1
L32
8.2
R100
0
R107 470
R103
OPEN
C181
33/10
C180 0.1
Z34
1
2
3
6
7
8
C18
33/10
36
Z31
1
2
3
6
7
8
53
VssQ_4
54
D5
55
VccQ_4
56
D4
57
D3
58
D2
59
D1
60
D0
61
A0
62
A1
63
A2
64
VssQ_5
65
A3
66
VccQ_5
67
A4
68
A5
69
A6
70
A7
71
A8
72
A9
73
A10
74
A11
75
VssQ_6
76
A12
77
VccQ_6
78
A13
79
A14
80
A15
81
A16
82
A17
83
A18
84
A19
85
A20
86
VssQ_7
87
A21
88
VccQ_7
89
A22
90
A23
91
VSS_2
92
A24
93
VCC_2
94
A25
95
BS/PTK[4]
96
RD
33
45
45
45
45
36
Z17
1
2
36
7
8
Z20
33
33
33
33
33
33
33
1
2
3
6
7
8
Z21
1
2
3
6
7
8
Z22 1
2
3
6
7
8
Z23 1
2
3
6
7
8
Z24 1
2
3
6
7
8
Z25 1
2
3
6
7
8
Z26 1
2
3
6
4
5
4
5
4
5
4
5
4
5
4
5
4
5
7
8
5
6
7
8
9
4-3-1
<LOCATION MARK>
(Refer to the page 4-3-2.)
(Refer to the page 4-3-4.)
(Refer to the page 4-3-3.)
(Refer to the page 4-3-5.)
• The Location Mark indicated in each Schematic Diagram of Ether Board (2/3) is as follows.
<Example>
For Schematic Diagram
of Ether Board (2/3) [
1
] :
• The Schematic Diagram of Ether Board (2/3) is described by 4 partitions.
• When connecting all the Schematic diagram, refer to this Partition Diagram.
Location of each Schemaitc diagram is marked (           ) in the diagram.
Location Mark
ETHER BOARD (2/3)
A
10
11
12
13
14
15
16
17
18
B
C
D
E
PARTITION DIAGRAM FOR SCHEMATIC DIAGRAM 
OF ETHER BOARD (2/3)
Page of 59
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