Panasonic WV-CU950 Service Manual ▷ View online
<LOCATION MARK>
PLD
DATA[31-0]
ADDR[25-0]
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
ADDR[25]
ADDR[24]
ADDR[23]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
nRD
nBS
nCS[0]
nWE[3-0]
nWE[1]
nWE[0]
nCS[2]
LED0
LED1
LED2
LED3
DBG_LED0
DBG_LED1
DBG_LED2
DBG_LED3
BOOTSEL0
BOOTSEL1
MAC_RDY
MAC_AEN
nUDS
nMAC_WR
nMAC_RD
nLDS
nWAIT
MAC_SPEED
MAC_ACT
MAC_LINK
nPROM_CS
nFLASH_WE
nFLASH_OE
nFLASH_ACC
PLD_CLK
MAC_RST
nMAC_CS
nMAC_IRQ
nMAC_IOCS16
nFLASH_BUSY
nFLASH_CS
ADDR[25-0]
DATA[31-0]
IC16
1
GND_1
2
TDI
3
VCCO0_1
4
B0
5
B1
6
B2
7
B4
8
B5
9
B6
10
GND[Bank0]_1
11
B8
12
B9
13
B10
14
B12
15
B13
16
B14
17
VCCO0_2
18
C14
19
C13
20
C12
21
C10
22
C9
23
C8
24
GND[Bank0]_2
25
C6
26
C5
27
C4
28
C2
29
C0
30
VCCO0 3
67
VCCO1 2
68
F0
69
F1
70
F2
71
F4
72
F5
73
F6
74
GND[Bank1]_3
75
F8
76
F9
77
F10
78
F12
79
F13
80
F14
81
VCCO1_3
82
G14
83
G13
84
G12
85
G10
86
G9
87
G8
88
GND[Bank1]_4
89
G6
90
G5
91
G4
92
G2
93
G0
94
VCCO1_4
95
TDO
96
VCC_3
97
GND_4
98
H14
99
H13
100
H12
101
H10
102
H9
103
H8
104
GND[Bank1]_5
105
VCCO1_5
106
H6
107
H5
108
H4
109
H2
110
H1
111
H0/GOE1
112
CLK3/I
113
GND[Bank0]_4
114
CLK0/I
115
VCC_4
116
A0/GOE0
117
A1
118
A2
119
A4
120
A5
121
A6
122
VCCO0_5
123
GND[Bank0]_5
124
A8
125
A9
126
A10
127
A12
128
A14
3R3V
L34
2.2
C89
0.1
C87
0.1
C85
0.1
C80
0.1
C81
0.1
C82
0.1
C83
0.1
C94
0.1
C93
0.1
C92
0.1
nWE[3-0]
RD/nWR
nRD
nBS
nWAIT
nFLASH_CS
nFLASH_OE
nFLASH_BUSY
nFLASH_ACC
nFLASH_WE
RESETOUT
nRESETP
PLD_CLK
C90
33/10
TD78
TD73
TD74
TD75
TD76
TD77
R133
OPEN
R135
OPEN
R134
OPEN
OPEN
nPROM_CS
BOOTSEL0
BOOTSEL1
R125
OPEN
Z40
1
2
3
45
6
7
8
Z44
22
1
2
3
4
5
6
7
8
R116
22
R118
22
R130
22
22
R128
22
TD72
TD71
R129
10k
TD65
TD64
R120
10k
R121
10k
R123
22
Z37
22
1
2
3
4
5
6
7
8
R122
10k
R124
OPEN
TD95
R229
10k
R230
10k
R231
10k R232
10k
DGND
R240
10k
R136
1k
R137
1k
R138
1k
ETHER BOARD (2/3)
C
D
E
4-3-2
SCHEMATIC DIAGRAM OF ETHER BOARD (2/3) [
1
]
<LOCATION MARK>
MAC
JK1
10/100 BASE-T
CONNECTOR
10/100 BASE-T
CONNECTOR
MAC/PHY_CLK
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
DATA[12]
DATA[13]
DATA[14]
DATA[15]
ADDR[10]
ADDR[9]
ADDR[8]
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
nUDS
nMAC_WR
nMAC_RD
MAC_RST
nMAC_CS
nMAC_IRQ
IC17
1
NC1
2
DTACK
3
RESET
4
LDS
5
SA[1]
6
SA[2]
7
SA[3]
8
SA[4]
9
SA[5]
10
SA[6]
11
SA[7]
12
SA[8]
13
VDD1
14
VSS1
15
SA[9]
16
IRO
17
NC2
18
R/W
19
NC3
20
NC4
21
NC5
22
UDS
23
SD[15]
24
SD[14]
25
SD[13]
26
SD[12]
27
VDD2
28
VSS2
29
SD[11]
30
SD[10]
31
SD[9]
32
SD[8]
33
SD[7]
70
TPIP
71
TPIN
72
VSSA3
73
VDDA3
74
REXTBS
75
VSSA4
76
VDDM
77
VSSM1
78
VDDPD
79
LCLK/XTALIN
80
XTALOUT
81
VSSPD
82
VDDA4
83
REXT100
84
REXT10
85
VSSA5
86
VSSO1
87
TPON
88
TPOP
89
VSSO2
90
VSSO3
91
VDDO
92
ZVREG
93
VSSM2
94
VSS8
95
RXD[0]
96
RXD[1]
97
RXD[2]
98
RXD[3]
99
RX_CLK
100
CRS
101
COL
102
RX_DV
103
GP[0]/LINK
104
VDD6
105
VSS9
106
GP[1]/DPX
107
TX_CLK
108
TX_EN
109
TXD[0]
110
TXD[1]
111
TXD[2]
112
TXD[3]
113
GPI[2]/SPD
114
VDD7
115
VSS10
116
I_OP
117
IO_BASE[0]
118
IO_BASE[1]
119
IO_BASE[2]
120
GPO[0]
121
NC7
122
NC8
123
NC9
124
NC10
125
NC11
126
VDD8
127
VSS11
128
CS
3R3V
3R3V
X3
(25 MHz)
1
CONT
2
GND
3
OUT
4
VDD
R173
10k
R163
0
R169
1.8k
R170
1.8k
R166
24k
R164
20k
R168
100
R174
0
R177
49.9
R178
49.9
R180
560
R179
560
C107
33/10
C114
33/10
C116
33/10
33/10
C118
33/10
33/10
C121
22/16
C123
0.01
C97
0.1
C98
0.1
C110
C108
0.1
C120
0.1
C122
0.1
C119
0.1
0.1
C111
0.1
C117
0.1
C115
0.1
C124
1000p
R176
49.9
R175
49.9
R171
180
R172
180
180
L36
2.2
L37
2.2
L39
2.2
L38
2.2
C112
1000p
C113
1000p
C100
0.1
C105
0.1
C106
33/10
R153
10k
R154
10k
R155
10k
R156
OPEN
R149
OPEN
R150
OPEN
R151
OPEN
C125
1000p
1000p
TD80
TD81
TD82
TD84
C109
0.1
3R3V
L40
2.2
R140
0
R139
OPEN
R143
OPEN
R144 0
Z51
OPEN
1
2
3
6
7
8
Z50
OPEN
1
2
3
6
4
5
4
5
7
8
Z49 1
2
3
6
7
8
Z48 1
2
3
6
4
5
4
5
7
8
R145
OPEN
R146
OPEN
R142
0
0
0
R141
0
R147
1k
C183
0.1
R165
2.4k
DGND
DGND
DGND
DGND
DGND
JK1
1
TD+
2
TD-
3
CTT
4
CHS GROUND
5
CHS GROUND
6
CTR
7
RD+
8
RD-
9
LEDAN1
10
I_ACT
11
I_LINK
12
LEDAN2
Attachment1
Attachment2
/AEN
/RDY
/SA[0]
/*IOWR
/*IORD
/*BHE
10/100 BASE-T
ETHER
BOARD
(2/3)
BOARD
(2/3)
<INDEX>
IC16
C11,C12,
D11,D12
D11,D12
IC17
C15,C16,
D15,D16
D15,D16
IC18
B15
Q3
A13,B13
Q4
A13
Q5
A13
Q6
A13
Q7
A13
Q8
A13
Q9
A13
Q10
A13
D13
A11,A12
D14
A11,A12
D15
B13
D16
A13
D17
A13
D18
A13
D19
A13
D20
A13
D21
A13
D22
A13
4-3-3
SCHEMATIC DIAGRAM OF ETHER BOARD (2/3) [
2
]
4-3-4
SCHEMATIC DIAGRAM OF ETHER BOARD (2/3) [
3
]
<LOCATION MARK>
DIP SW
WRITE
(CN)
(CN)
nCS[0,2,3,4,5,6]
nCS[0]
nCS[4]
nCS[5]
nCS[6]
nWE[1]
nCS[2]
LED0
LED1
LED2
LED3
DBG_LED0
DBG_LED1
DBG_LED2
DBG_LED3
IO[7-0]
IO[0]
IO[1]
IO[2]
IO[3]
IO[4]
IO[5]
IO[6]
IO[7]
IO[7]
IO[6]
IO[3]
IO[5]
IO[4]
IO[2]
IO[1]
IO[0]
PLD_TDD
PLD_TCK
PLD_TMS
nEXT_CS
nEXT_RESET
nEXT_BUFEN
IRQ[0]
PLD_TDI
C6
26
C5
27
C4
28
C2
29
C0
30
VCCO0_3
31
TCK
32
VCC_1
33
GND_2
34
D14
35
D13
36
D12
37
D10
38
D9
39
D8
40
GND[Bank0]_3
41
VCCO0_4
42
D6
43
D5
44
D4
45
D2
46
D1
47
D0
48
CLK1/I
49
GND[Bank1]_1
50
CLK2/I
51
VCC_2
52
E0
53
E1
54
E2
55
E4
56
E5
57
E6
58
VCCO1_1
59
GND[Bank1]_2
60
E8
61
E9
62
E10
63
E12
64
E14
65
GND_3
66
TMS
67
VCCO1_2
68
F0
69
F1
70
F2
71
F4
F5
C83
0.1
C84
0.1
C86
0.1
C88
0.1
C95
0.1
C94
0.1
nCS[0,2,3,4,5,6]
RD/nWR
C91
33/10
C96
33/10
TD73
TD74
TD75
TD76
TD77
TD70
TD69
TD68
TD67
TD66
IRQ[5-0]
Z45
1
2
3
6
4
5
4
5
7
8
Z46
1
2
3
6
7
8
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
D15
D16
D17
D18
D19
D20
D21
D22
SW3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Z41
1
2
3
4
5
6
7
8
Z39
10k
10k
1
2
3
4
5
6
7
8
D13
1
2
3
4
5
D14
1
2
3
4
5
CN9
1
VCC
2
TDD
3
TDI
4
ISPEN
NC
5
6
TMS
7
GND
8
TCK
3R3V
L35
8.2
R131
10k
R132
10k
Z36
22
1
2
36
45
7
8
R119
22
R117
22
R126
22
R127
22
R114
10k R115
10k
Z38
10k
680
680
10k
10k
1
2
3
4
5
6
7
8
TD94
C182
0.1
DGND
DGND
Z42
1
2
3
6
7
8
Z43
1
2
3
6
4
5
4
5
7
8
WDT_DIS
A
10
11
12
13
B
C
<LOCATION MARK>
SERIAL ROM (MAC ADDRESS)
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
VSS2
29
SD[11]
30
SD[10]
31
SD[9]
32
SD[8]
33
SD[7]
34
VSS3
35
SD[6]
36
SD[5]
37
SD[4]
38
SD[3]
39
SD[2]
40
VDD3
41
SD[1]
42
SD[0]
43
VSS4
44
CLKO25M
45
BIST
46
IDDQ
47
TEST2
48
EEDO
49
EEDI
50
EECK
51
EECS
52
VSS5
53
VDD4
54
VSS6
55
VSSA1
56
VDDA1
57
VDD5
58
CPU[0]
59
CPU[1]
60
I_LINK
61
I_SPEED
62
I_ACT
63
VSS7
64
NC6
65
TEST1
66
MDIO
67
MDC
68
VSSA2
69
VDDA2
70
TPIP
71
TPIN
72
VSSA3
73
VDDA3
74
REXTBS
VSSA4
IC18
1
NC1
2
VCC
3
CS
4
SK
5
DI
6
DO
7
GND
8
NC2
R173
10k
R152
10k
R167
10k
R169
1.8k
R170
1.8k
R166
24k
C99
0.1
C102
0.1
C110
0.1
C120
0.1
R159
OPEN
R161
10k
C101
0.1
R157
OPEN
R148
10k
TD79
TD83
C103
0.1
C104
33/10
C109
0.1
R158
10k
Z47
10k
1
2
36
45
7
8
R160
10k
R162
OPEN
C184
0.1
DGND
DGND
DGND
Attachment2
14
15
16
17
18
4-3-5
SCHEMATIC DIAGRAM OF ETHER BOARD (2/3) [
4
]
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