Panasonic WV-CU950 Service Manual ▷ View online
4-1-4
SCHEMATIC DIAGRAM OF MAIN BOARD [
3
]
SW2
MODE
SELECTION
SWITCHES
MODE
SELECTION
SWITCHES
SW1
CONTROLLER
NUMBER
SWITCH
CONTROLLER
NUMBER
SWITCH
CN2
SERIAL
PORT
SERIAL
PORT
JK1
DATA
PORTS
DATA
PORTS
<LOCATION MARK>
PKEY[1]
PKEY[3]
PKEY[2]
PKEY[6]
PKEY[7]
PKEY[5]
PKEY[0]
PKEY[1]
PKEY[2]
PKEY[3]
/RS485RX_EN
COL_DET
RS485TX_EN
PKEY[0]
RS485_TX
RS485_RX
RS232C_RX
RS232C_TX
RS232C_EN
D2
1
2
3
4
5
IC7
1
1A
2
1B
3
1CLR
4
1Q
5
2Q
6
2Cext
7
2Rext/Cext
8
GND
9
2A
10
2B
11
2CLR
12
2Q
13
1Q
14
1Cext
15
1Rext/Cext
16
Vcc
JK1
JK1
1
GND
2
TB
3
TA
4
RB
5
RA
6
GND
7
GND
8
TB
9
TA
10
RB
11
RA
12
GND
Attachment1
Attachment2
CF1
1
2
3
4
5
6
7
8
9
10
VS4
DGND
R26
4.7
C47
100p
R51
36k
VS6
R55
36k
R60
10k
VS2
SW2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C60
0.1
Z23
1
2
36
45
7
8
R50
36k
R34
4.7
R57
150k
C42
1
DGND
D17
C45
100p
DGND
C59
0.1
D16
C41
47/16
D12
R52
2.2k
2.2k
R59
150k
D14
R35
4.7
1/4W
1/4W
D5
1
2
3
R42
150
1/2W
DGND
D11
R44
2.2k
VS1
R27
4.7
1/4W
1/4W
DGND
SW1
1
1
9
C_1
2
2
8
8
4
4
10
C_2
R53
2.2k
2.2k
R54
36k
D15
10K
D6
1
2
3
VS5
D7
1
2
3
R43
2.2k
IC9
1
NC1
2
R
3
RE
4
DE
5
D
6
GND1
7
GND2
8
NC2
9 Y
10 Z
11 B
12 A
13
11 B
12 A
13
VCC1
14
VCC2
D4
1
2
3
CF2
1
2
3
4
5
6
7
8
9
10
R58
10k
DGND
IC8
1
VDD
2
C1+
3
VCC
4
C1-
5
C5+
6
C5-
7
DIN1
8
DIN2
9
ROUT1
10
ROUT2
11
RIN2
12
RIN1
13
DOUT2
14
DOUT1
15
VCHA
16
STBY
17
VSS
18
C4-
19
GND
20
C4+
C46
100p
D10
CN2
CN2
1
CD
2
RD
3
SD
4
ER
5
SG
6
DR
7
RS
8
CS
9
CI
Attachment1
Attachment2
VS3
D13
D1
1
2
3
4
5
IC10
1
NC1
2
R
3
RE
4
DE
5
D
6
GND1
7
GND2
8
NC2
9 Y
10 Z
11 B
11 B
12 A
13
VCC1
14
VCC2
C55
0.1
C57
0.1
C51
0.1
C62 0.1
C52
OPEN
C54
3.3/35
C63
3.3/35
C53
3.3/35
C64
3.3/35
RA
RB
TA
TB
12
11
10
9
8
7
11
10
9
8
7
6
5
4
3
2
1
5
4
3
2
1
5
4
3
2
1
4
3
2
1
9
8
7
6
8
7
6
DATA
SERIAL
MODE
CONTROLLER
NO.
1
A
B
C
D
2
3
4
5
6
4-1-5
SCHEMATIC DIAGRAM OF MAIN BOARD [
4
]
ADDRESS
DECODE
DECODE
KEY SCAN
LED CONTROL
LCD CONTRAST
CONTROL
CONTROL
TO
JOYSTICK
SWITCH
BOARD
CN204
JOYSTICK
SWITCH
BOARD
CN204
CN7
JOYSTICK
CONNECTOR
JOYSTICK
CONNECTOR
TO
PANEL
BOARD
E101
PANEL
BOARD
E101
TO
PANEL
BOARD
E102
PANEL
BOARD
E102
TO
FUNCTION
SWITCH
BOARD
CN601
FUNCTION
SWITCH
BOARD
CN601
TO
ETHER
BOARD
CN1
ETHER
BOARD
CN1
<LOCATION MARK>
KEYS[0]
KEYS[1]
KEYS[2]
AD[4]
AD[7]
AD[5]
AD[6]
AD[0]
AD[1]
AD[2]
AD[3]
A[17]
A[18]
A[19]
A[18]
/RS485RX_EN
COL_DET
RS485TX_EN
KEYS[3]
KEYS[3]
KEYS[2]
KEYS[1]
KEYS[0]
PKEY[7]
PKEY[6]
PKEY[5]
PKEY[4]
PKEY[3]
PKEY[2]
PKEY[1]
PKEY[0]
RS485_TX
RS485_RX
/RS485RX_EN
RS485_TX
RS485_RX
RS232C_RX
RS232C_TX
RS232C_EN
AD[5]
AD[6]
AD[4]
AD[7]
AD[2]
AD[3]
AD[0]
AD[1]
PLED[0]
PLED[1]
PLED[2]
PLED[3]
PLED[4]
PLED[5]
LLAT[0-1]
LLAT[0]
LLAT[1]
LLAT[0]
LLAT[1]
FLASH/PROM
A[19]
A[16]
A[15]
A[0]
KEYS[0-3],PKEY[0-7]
DB[0]
PROM/CS
SMALL/LARGE
PKEY[0]
LCD_SMALLCS
A[15]
LCD_CNT
LCD_SMALLCS
LED_LAT
LED_DATA
VSW
PAN
TILT
ZOOM
A5V
A[16]
LCD_LARGE/CS
PLED[0]
PLED[1]
PLED[2]
PLED[3]
PLED[4]
PLED[5]
/WR
/RD
LCD-CONTRAST
SRAM1/CS
SRAM2/CS
FLASH/CS
/SWAP
/SWAP
R82
1M
R70
39k
R94
2.2
2.2
2.2
C105
OPEN
R95
1
2
3
DGND
L10
IC21
9
A
10
B
8
Y
C87
0.1
Z34
100
100
100
100
1
2
3
6
4
5
7
8
C102 OPEN
DGND
D30
D29
D28
D27
D26
D25
D24
1
2
3
1
2
3
CN10
1
2
GND
3
PLED[0]
4
PLED[1]
5
PLED[2]
6
PLED[3]
7
PLED[4]
8
PLED[5]
9
LLAT[0]
10
LLAT[1]
11
/RST
Attachment1
Attachment2
C81
0.1
C79
0.1
0.1
R71
30k
Z35
1
2
3
6
4
5
7
8
DGND
IC22
9
A
10
B
11
C
8
Y
C101 OPEN
CN6
1
9V
2
9V
3
9V
4
GND
5
GND
6
GND
7
TX
8
RX
9
SGND
10
/RST
11
GX_STATUS
12
GXCOM_Enable
Attachment1
Attachment2
R79
1M
IC24
1
CLR
2
1Q
3
1D
4
2D
5
2Q
6
3Q
7
3D
8
4D
9
4Q
10
GND
11
CLK
12
5Q
13
5D
14
6D
15
6Q
16
7Q
17
7D
18
8D
19
8Q
20
VCC
IC14
1
A
2
B
3
C
4
G2A
5
G2B
6
G1
7
Y7
8
GND
9
Y6
10
Y5
11
Y4
12
Y3
13
Y2
14
Y1
15
Y0
16
VCC
1
2
3
R98
100
IC33
1
IN+
2
VSS
3
IN-
4
OUT
5
VDD
C72
0.1
0.1
L9
C76
1
D23
DGND
R81
1M
1
2
3
R97
OPEN
R77
1M
DC_IN
Z36
1
2
3
6
4
5
7
8
DGND
IC20
1
CLR
2
1Q
3
1D
4
2D
5
2Q
6
3Q
7
3D
8
4D
9
4Q
10
GND
11
CLK
12
5Q
13
5D
14
6D
15
6Q
16
7Q
17
7D
18
8D
19
8Q
20
VCC
R89
2.2
L6
R100
100
C114
33/10
DGND
Q10
IC25
5
6
7
Q9
IC18
1
A
2
B
3
C
4
G2A
5
G2B
6
G1
7
Y7
8
GND
9
Y6
10
Y5
11
Y4
12
Y3
13
Y2
14
Y1
15
Y0
16
VCC
DGND
C73
(2/3)
(2/5)
(1/5)
(3/5)
(3/5)
(3/4)
(4/5)
(1/4)
(2/4)
(1/5)
(3/3)
R92
2.2
IC22
1
A
2
B
13
C
12
Y
L12
IC19
1
1G
2
1A
3
1B
4
1Y0
5
1Y1
6
Y12
7
1Y3
8
GND
9
2Y3
10
2Y2
11
2Y1
12
2Y0
13
2B
14
2A
15
2G
16
VCC
R91
2.2
C100 OPEN
C104 OPEN
IC13
1
A
2
B
3
C
4
G2A
5
G2B
6
G1
7
Y7
8
GND
9
Y6
10
Y5
11
Y4
12
Y3
13
Y2
14
Y1
15
Y0
16
VCC
Z33
1
2
3
6
7
8
R101
0
Z26
1
2
3
6
4
5
7
8
IC31
9
A
10
B
8
Y
R78
1M
1
2
3
DGND
C80
R68
10k
5V
C
4
G2A
5
G2B
6
G1
7
Y7
8
GND
9
Y6
10
Y5
11
Y4
12
Y3
13
Y2
Y1
DGND
L11
R76
2.2k
DGND
CN8
1
VSS
2
VDD
3
VO-SMALL
4
RS
5
R/W
E
6
7
DB0
8
DB1
TH1
OPEN
IC31
1
A
2
B
3
Y
R87
1A
L7
R75
OPEN
CN9
1
5V
5V
2
GND
3
PKEY[0]
4
PKEY[1]
5
PKEY[2]
6
PKEY[3]
7
PKEY[4]
8
PKEY[5]
9
PKEY[6]
10
PKEY[7]
11
KEYS[0]
12
KEYS[1]
13
KEYS[2]
14
KEYS[3]
Attachment1
Attachment2
10K
R99
100
DGND
R93
2.2
C99
0.1
C103
OPEN
R80
1M
R64
1k
D22
1
2
3
VS7
OPEN
CN7
1
5V
2
PAN
3
GND
4
MCHP
5
KEYS-Y3
6
TILT
7
ZOOM
8
VSW
Attachment1
Attachment2
IC31
4
A
5
B
6
Y
IC31
12
A
13
B
11
Y
DGND
1
2
3
IC11
1
A
2
B
3
C
4
G2A
5
G2B
6
G1
7
Y7
8
GND
9
Y6
10
Y5
11
Y4
12
Y3
13
Y2
14
Y1
15
Y0
16
VCC
DGND
R90
2.2
DGND
IC21
1
A
2
B
3
Y
L8
R74
10k
DGND
IC22
3
A
4
B
5
C
6
Y
100
4
5
R83
1M
DGND
IC25
8
V+
4
V-
DC_IN
C70
0.1
C89
0.1
C113
0.1
F/P /SWAP
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
0
A19
1
1
1
0
0
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
1
A19 A18
0
0
0
0
1
1
A18
0
1
0
1
0
1
A17
CN7
JOYSTICK
TD51
TD53
TD52
TD57
TD56
TD60
TD61
TD62
TD63
TD64
TD65
TD66
TD67
TD68
TD69
TD70
TD71
TD72
TD73
TD74
TD58
TD59
TD55
TD54
6
7
8
9
10
11
4-2-1
<LOCATION MARK>
(Refer to the page 4-2-2.)
(Refer to the page 4-2-4.)
(Refer to the page 4-2-3.)
(Refer to the page 4-2-5.)
• The Location Mark indicated in each Schematic Diagram of Ether Board (1/3) is as follows.
<Example>
For Schematic Diagram
of Ether Board (1/3) [
For Schematic Diagram
of Ether Board (1/3) [
1
] :
• The Schematic Diagram of Ether Board (1/3) is described by 4 partitions.
• When connecting all the Schematic diagram, refer to this Partition Diagram.
• When connecting all the Schematic diagram, refer to this Partition Diagram.
Location of each Schemaitc diagram is marked ( ) in the diagram.
Location Mark
ETHER BOARD (1/3)
1
A
B
C
D
E
F
2
3
4
5
6
7
8
9
PARTITION DIAGRAM FOR SCHEMATIC DIAGRAM
OF ETHER BOARD (1/3)
<LOCATION MARK>
CPU_CLK(48MHz)
TO
MAIN
BOARD
CN6
MAIN
BOARD
CN6
CLK_BUF
CPU
3.3V
/
5V BUF
5V
/
3.3V BUF
nRESETP
CPU_TDO
nASEBRKAK
IRQ[5]
CPU_TCK
CPU_TMS
CPU_TDI
STATUS0
STATUS1
UC_TX
nTRST
RS232C_TXD
RS485_TXD
UC_RX
RS232C_RXD
RS485_RXD
CN1
1
Vcc_+9V
2
Vcc_+9V
3
Vcc_+9V
4
GND
5
GND
6
GND
7
TX
8
RX
9
SGND
10
RST
IC2
1
1OE
2
1A
3
1Y
4
2OE
5
2A
10
3OE
11
4Y
12
4A
13
4OE
14
VCC
R10
4.7k
C40
0.1
R68
10k
DGND
DGND
R64
10k
PLD_CLK
C53
0.1
C6
0.1
R70
10k
R48
10k
R12
680
C45
0.1
C12
0.1
POW9V
CN4
1
3.3V
2
TxD
3
RxD
4
GND
5
485Tx
6
485Rx
Attachment1
Attachment2
3R3V
C33
0.1
TD36
R72
4.7k
L10
2.2
IC5
1
G1
2
A1
3
Y2
4
GND
5
A2
6
Y1
7
G2
8
VCC
R21
10k
IC7
1
NC
2
IN_A
3
GND
4
OUT_Y
5
VCC
R56
22
R46 10k
C51
0.1
IC3
1
NC
2
IN_A
3
GND
4
OUT_Y
5
VCC
R226
4.7k
C30
33/10
R45
10k
C48
100p
C42
0.1
nWAIT
R19
100k
CN5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R224
10k
R14
100k
R50
0
C11
33/10
Q1
R55
OPEN
L17
8.2
TD33
DGND
IC1
1
NC
2
IN_A
3
GND
4
OUT_Y
5
VCC
C43
470p
R242
OPEN
DGND
R2
22
R241
10k
C34
0 1
R74
4.7k
R49
0
R37
22
R58
OPEN
R8
1A
UC_RESET
TD37
R71
10k
R47 10k
L8
2.2
C44
470p
TD34
WDT_EN
X1
(48.000MHz)
1
CONT
2
GND
3
OUT
4
VDD
3R3V
C46
100p
3R3V
R3
0
DGND
C13
0.1
R53
22
R1
22
R36
OPEN
5V
R11
680
R41
10k
IC9
1
REF
2
CLK2
3
CLK1
4
GND
5
CLK3
6
VDD
7
CLK4
8
CLKOUT
R59
OPEN
R222
10k
R76
22
R73
10k
WDT_CLK
L6
2.2
C32
100p
C25
0.1
R66
10k
C16
0.1
R225 10k
TD38
L16
2.2
C31
0.1
R77
22
R60
10k
DGND
R62
4.7k
Q2
C38
33/10
R63
10k
DGND
IC8
1
1A
2
1B
13
4B
14
VCC
R22
10k
D2
C29
0.1
R57
22
D1
TD35
R75
22
IC12
WE2/D
WE3/D
PTE[7
AFE_HC
AFE_RLYCNT
AFE_
PTM[7]/PINT[7]/AFE_FS/USB1d_RCV
PTM[6]/PINT[6]/AFE_RXIN/USB1d_SPEED
PTM[5]/PINT[5]/AFE_TXOUT/USB1d_TXSE0
121
PTM[4]/PINT[4]/AFE
RDET/
122
RESERVED/USB1d_SUSPEND
123
USB1_ovr_crnt/USBF_VBUS
124
USB2__ovr_crnt
125
RTS2/USB1d_TXENL
126
PTE[2]/USB1_pwr_en
127
PTE[1]/USB2_pwr_en
128
CKE/PTK[5]
129
RAS3/PTJ[0]
130
RESERVED/PTJ[1]
131
RESERVED/CAS/PTJ[2]
132
VssQ_10
133
RESERVED/PTJ[3]
134
VccQ_10
135
RESERVED/PTJ[4]
136
RESERVED/PTJ[5]
137
VSS_3
138
PTD[5]/CL1
139
VCC_3
140
PTD[7]/DON
141
PTE[6]/M_DISP
142
PTE[3]/FLM
143
PTE[0]/TDO
144
PCC0RESET/DRAK0
145
PCC0DRV/DACK0
146
WAIT
147
RESETM
148
ADTRG/PTH[5]
149
IOIS16/PTG[7]
150
ASEMD0
151
PTG[5]/ASEBRKAK
152
PTG[4]
153
PCC0BVD2/PTG[3]/AUDATA[3]
154
PCC0BVD1/PTG[2]/AUDATA[2]
155
VSS_4
156
PCC0CD2/PTG[1]/AUDATA[1]
157
VCC_4
158
PCC0CD1/PTG[0]/AUDATA[0]
159
VssQ_11
160
PTF[7]/PINT[15]/TRST
161
VccQ_11
162
PTF[6]/PINT[14]/TMS
163
PTF[5]/PINT[13]/TDI
164
PTF[4]/PINT[12]/TCK
165
PTF[3]/PINT[11]/RESERVED
166
PCCREG/PTF[2]/RESERVED
167
PCC0VS1/PTF[1]/RESERVED
168
PCC0VS2/PTF[0]/RESERVED
169
MD0
170
Vcc_PLL1
171
CAP1
172
Vss_PLL1
173
Vss_PLL2
174
CAP2
175
Vcc_PLL2
176
PCC0WAIT/PTH[6]/AUDCK
177
VSS_5
178
VCC_5
179
XTAL
180
EXTAL
181
LCD15/PTM[3]/PINT[10]
182
LCD14/PTM[2]/PINT[9]
183
LCD13/PTM[1]/PINT[8]
184
LCD12/PTM[0]
185
STATUS0/PTJ[6]
186
STATUS1/PTJ[7]
187
CL2/PTH[7]
188
VssQ_12
189
CKIO
190
VccQ_12
191
TXD0/SCPT[0]
192
SCK0/SCPT[1]
193
TXD_SIO/SCPT[2]
194
SIOMCLK/SCPT[3]
195
TXD2/SCPT[4]
196
SCK_SIO/SCPT[5]
197
SIOFSYNC/SCPT[6]
198
RXD0/SCPT[0]
199
RXD_SIO/SCPT[2]
200
VSS_6
201
RXD2/SCPT[4]
202
VCC_6
203
SCPT[7]/CTS2/IRQ5
204
LCD11/PTC[7]/PINT[3]
205
LCD10/PTC[6]/PINT[2]
206
LCD9/PTC[5]/PINT[1]
207
VssQ_13
208
LCD8/PTC[4]/PINT[0]
209
VccQ_13
210
LCD7/PTD[3]
R40
33
ETHER BOARD (1/3)
D
E
F
4-2-2
SCHEMATIC DIAGRAM OF ETHER BOARD (1/3) [
1
]
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