Sony CDX-G3000UE / CDX-G3000UP / CDX-G3000UV / CDX-G3050UP / CDX-G3050UV / CDX-G3070UV Service Manual ▷ View online
CDX-G3000UE/G3000UP/G3000UV/G3050UP/G3050UV/G3070UV
CDX-G3000UE/G3000UP/G3000UV/G3050UP/G3050UV/G3070UV
25
25
4-6. SCHEMATIC DIAGRAM - MAIN Section (4/4) -
• See page 19 for Waveforms. • See page 26 for IC Pin Function Description.
(2/4)
1
6
MAIN
BOARD
(3/4)
BOARD
MAIN
4
MAIN
BOARD
(1/4)
6
5
0
0
3.3
3.3
0
0
3.3
0
0
2.4
2.5
3.3
3.2
3.3
3.2
3.3
3.3
0
3.3
1.6
3.3
0.1
0
3.3
3.3
3.3
3.3
1.4
3.3
0
1.3
1.5
0
3.3
0
0
0
0
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
0
(0)
3.3
3.3
3.3
2.9
3.3
(3.3)
2.1
(0)
(0)
(3.3)
(3.3)
(3.3)
C526
0.1
R551
100k
0.01
C521
100
R568
100k
R546
10k
R519
0
R1362
10k
R549
FB804
100k
R522
220k
R542
C534
47p
0.1
C1361
JL716
1k
R525
JL714
CL697
100
R528
100
R1337
32.768KHz
X501
CL502
100k
R512
100k
R511
CL645
R581
100k
100k
R561
0.1
C1363
22p
C527
100k
R560
CL666
30k
R524
100
R1336
1k
R506
100k
R521
C530
3p
CL642
100k
R563
10k
R523
0.01
C533
100
R531
100
R529
R584
22
100
R1340
C551
2.2
100k
R514
JL502
FB81
1
100
R573
R500
100k
1000p
C520
R583
4.7k
R565
68k
R545
0
CL646
0.01
C523
100
R574
CL641
JL717
100
R1331
10k
R520
1
2
X502
LRB751V
-40T1G
D500
33k
R539
JL715
CL647
CL664
0.01
C531
100k
R502
0.01
C522
1000p
C501
33k
R536
6.3V
220
C550
33k
R533
0
R576
1k
R535
CL667
470
R526
100
R530
100
R572
IC501
1
NC
2
NC
3
NC
4
TEST
5
RESET
6
XT1
7
XT2
8
VSS1
9
CF1
10
CF2
11
VDD1
12
DEBUG_1
13
DEBUG_2
14
DEBUG_3
15
DEBUG_4
16
DEBUG_5
17
EN_USB
18
FL
T
19
EN_SYS
20
SDO
21
SDI
22
SCK
23
NC
24
NC
25
SYNC_OUT
26
RX
27
TX
28
CTRL1_A
29
CTRL1_B
30
CTRL1_C
31
CTRL2_A
32
CTRL2_B
33
CTRL2_C
34
BUSY
35
BU_IN
36
VSS2
37
VDD2
38
HIT2_CLK
39
HIT2_DATA
40
HIT2_RST
41
CMD_ERR
42
CE
43
SYSRST
44
USBIN
45
WDT_MON
46
LCD_CLK
47
LCD_CE
48
LCD_SO
49
NC
50
NC
51
ACC_IN
52
VDD3
53
VSS3
54
TELA
TT
55
NC
56
AT
T
57
AMP_MUTE
58
AMPSTB
59
S-GAIN_A
60
S-GAIN_B
61
S-GAIN_C
62
KEY_ACK0
63
KEY_ACK1
64
SIRCS
65
NC
66
DUBUG_6
67
DUBUG_7
68
BEEP
69
NC
70
NC
71
RE-ON
72
RE_IN1
73
RE_IN0
74
NC
75
NC
76 NC
77 NC
78 KEYIN1
79 KEYIN0
80 RC_IN0
81 RC_IN1
82 MECHA_ON
83 NC
84 NC
85 VSS4
86 VDD4
87 NC
88 NC
89 NC
90 NOSE_SW
91 NC
92 NC
93 MEC_DSW
94 MEC_LSW
95 FILT
96 MEC_LOAD
97 MEC_INSW
98 MEC_SELFSW
99 DRV_ON
100 MEC_EJECT
JL503
CL500
1k
R537
C528
3p
0.01
C532
100k
R556
100
R1341
100
R567
100
R1338
LRB751V
-40T1G
D503
47p
C535
1000p
C502
CL665
100
R532
CL698
100
R569
CL501
1k
R527
100
R575
100
R1339
220k
R577
10k
R570
JL501
18p
C524
R544
1M
100k
R517
100
R1335
100k
R543
2.2
C1380
100k
R505
100k
R554
10M
R540
JL718
1000p
C503
CL668
100k
R503
R548
100k
BUIN
CTRL2
STBY
SELF
EN_USB
IN_SW
BEEP
0.1
C1354
EN_SYS
AMP_MUTE
L_SW
EJECT
DRV_ON
D_SW
LOAD
SYSRST
SIRCS
PANEL_DET
RXD1
CE
BUSY
KEY_1
ACC_IN
SYNC
FLT_USB
SDI
RC_IN0
CMD_ERR
SYSRST
SCK
USB_IN
KEY_0
SMONI
RE_1
RC_IN1
HIT2_SDA
RE_0
SDO
HIT2_SCL
HIT2_RST
S-GAIN_C
S-GAIN_B
S-GAIN_A
TXD1
CTRL1
IC501
27
26
18
4
(4/4)
19
3
20
6
MAIN BOARD
21
9.25MHz
23
5
7
LC88FC2H0AF2312-2H
25
2
SYSTEM CONTROLLER
24
22
15
6
12
J
3
G
13
4
F
5
2
7
C
H
I
11
14
E
9
B
8
A
10
D
1
(Page 23)
(Page 22)
(Page
24)
Ver. 1.2
Note: When IC501 on the MAIN board is replaced, the destination setting is necessary. Refer to “NOTE OF
REPLACING THE COMPLETE MAIN BOARD OR SYSTEM CONTROLLER (IC501)” on page 4.
CDX-G3000UE/G3000UP/G3000UV/G3050UP/G3050UV/G3070UV
CDX-G3000UE/G3000UP/G3000UV/G3050UP/G3050UV/G3070UV
26
26
• IC Pin Function Description
MAIN BOARD IC501 LC88FC2H0AF2312-2H (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1 to 3
NC
O
Not used
4
TEST
I/O
Not used
5
RESET
I
System reset signal input terminal “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
6
XT1
I
Low-speed clock signal input terminal (32.768 kHz)
7
XT2
O
Low-speed clock signal output terminal (32.768 kHz)
8
VSS1
-
Ground terminal
9
CF1
I
High-speed clock signal input terminal (9.25 MHz)
10
CF2
O
High-speed clock signal output terminal (9.25 MHz)
11
VDD1
-
Power supply terminal (+3.3V)
12 to 16
DEBUG_1 to
DEBUG_5
O
Not used
17
EN_USB
O
USB power on/off control signal output to the DC/DC converter “H”: power on
18
FLT
I
USB over current detection signal input from the DC/DC converter “L”: over current
19
EN_SYS
O
Power on/off control signal output to the DC/DC converter “H”: power on
20
SDO
O
Serial data output to the audio DSP
21
SDI
I
Serial data input from the audio DSP
22
SCK
O
Serial data transfer clock signal output to the audio DSP
23, 24
NC
O
Not used
25
SYNC_OUT
O
Frequency control signal output to the DC/DC converter
26
RX
I
Serial data input from the audio DSP
27
TX
O
Serial data output to the audio DSP
28, 29
CTRL1_A, CTRL1_B
O
Power on/off control signal output terminal Not used
30
CTRL1_C
O
Power on/off control signal output to the regulator
31
CTRL2_A
O
Power on/off control signal output to the regulator
32
CTRL2_B
O
Power on/off control signal output terminal Not used
33
CTRL2_C
O
Power on/off control signal output to the regulator
34
BUSY
I
Busy signal input from the audio DSP “L”: busy
35
BU_IN
I
Back-up power detection signal input terminal “L” is input at low voltage
36
VSS2
-
Ground terminal
37
VDD2
-
Power supply terminal (+3.3V)
38
HIT2_CLK
O
Serial data transfer clock signal output to the tuner unit
39
HIT2_DATA
I/O
Two-way data bus with the tuner unit
40
HIT2_RST
O
Reset signal output to the tuner unit “L”: reset
41
CMD_ERR
I
Command error signal input from the audio DSP “H”: error
42
CE
O
Chip enable signal output to the audio DSP
43
SYSRST
O
Reset signal output to the audio DSP “L”: reset
44
USBIN
I
USB device detection signal input from the audio DSP “L”: USB device is connected
45
WDT_MON
I
Watch-dog timer status monitor input from the audio DSP
46
LCD_CLK
O
Serial data transfer clock signal output to the front panel block
47
LCD_CE
O
Chip enable signal output to the front panel block
48
LCD_SO
O
Serial data output to the front panel block
49, 50
NC
O
Not used
51
ACC_IN
I
Accessory power detection signal input terminal “L”: accessory power on
52
VDD3
-
Power supply terminal (+3.3V)
53
VSS3
-
Ground terminal
54
TELATT
I
Telephone attenuator detection signal input terminal Not used
55
NC
O
Not used
56
ATT
O
Audio muting on/off control signal output terminal “H”: muting on
57
AMP_MUTE
O
Amplifi er muting on/off control signal output to the power amplifi er “L”: muting on
58
AMPSTB
O
Standby signal output to the power amplifi er “L”: standby
59 to 61
S-GAIN_A to
S-GAIN_C
O
SUB OUT gain control signal output terminal
62
KEYACK0
I
Key acknowledge signal (wake up signal) input from the rotary commander
63
KEYACK1
I
Key acknowledge signal (wake up signal) input from the front panel block
64
SIRCS
I
Remote control signal input from the front panel block
65
NC
O
Not used
Pin No.
Pin Name
I/O
Description
66, 67
DEBUG_6, DEBUG_7
O
Not used
68
BEEP
O
Beep sound drive signal output to the power amplifi er
69, 70
NC
O
Not used
71
RE_ON
O
Jog dial pulse pull-up signal output terminal
72, 73
RE-IN1, RE-IN0
I
Jog dial pulse input from the rotary encoder
74 to 77
NC
O
Not used
78, 79
KEYIN1, KEYIN0
I
Front panel key input terminal
80
RC_IN0
I
Rotary commander key input terminal
81
RC_IN1
I
Rotary commander shift key input terminal
82
MECHA_ON
I
Power detection signal input terminal for CD mechanism section
“H”: CD mechanism power on
“H”: CD mechanism power on
83, 84
NC
O
Not used
85
VSS4
-
Ground terminal
86
VDD4
-
Power supply terminal (+3.3V)
87 to 89
NC
O
Not used
90
NOSE_SW
I
Front panel remove/attach detection signal input terminal “L”: Front panel is attached
91, 92
NC
O
Not used
93
MEC_DSW
I
Chucking end detection switch input terminal
94
MEC_LSW
I
Limit in detection switch input terminal
95
FILT
I
Filter terminal for PLL
96
MEC_LOAD
O
Loading motor drive signal (loading direction) output terminal “H”: motor on
97
MEC_INSW
I
Disc insert detection switch input terminal
98
MEC_SELFSW
I
Self loading position detection switch input terminal
99
DRV_ON
O
Driver control signal output to the CD mechanism deck block
100
MEC_EJECT
O
Loading motor drive signal (eject direction) output terminal “H”: motor on
Ver. 1.2
CDX-G3000UE/G3000UP/G3000UV/G3050UP/G3050UV/G3070UV
27
Pin No.
Pin Name
I/O
Description
1
LFOUT
O
Audio signal (front L-ch) output terminal
2
LROUT
O
Audio signal (rear L-ch) output terminal
3
LVRIN
I
Audio signal (L-ch) input terminal
4
DACOUT_L
O
Audio signal (L-ch) output terminal
5
DACOUT_R
O
Audio signal (R-ch) output terminal
6
RVRIN
I
Audio signal (R-ch) input terminal
7
RROUT
O
Audio signal (rear R-ch) output terminal
8
RFOUT
O
Audio signal (front R-ch) output terminal
9
L1_IN
I
Audio signal (tuner L-ch) input terminal
10
R1_IN
I
Audio signal (tuner R-ch) input terminal
11
L2_IN
I
Audio signal (L-ch) input terminal Not used
12
R2_IN
I
Audio signal (R-ch) input terminal Not used
13
L3_IN_P
I
Audio signal (AUX L-ch) input terminal (positive)
14
L3_IN_N
I
Audio signal (AUX L-ch) input terminal (negative)
15
R3_IN_P
I
Audio signal (AUX R-ch) input terminal (positive)
16
R3_IN_N
I
Audio signal (AUX R-ch) input terminal (negative)
17, 18
ATEST01 (OPN),
ATEST02 (OPN)
-
Analog test terminal Not used
19
VREFOUT
O
Reference voltage output terminal Not used
20
VREF_ADC
-
External capacitor connection terminal for audio A/D converter reference voltage
21
AVSS2
-
Ground terminal (analog system)
22
AVDD2
-
Power supply terminal (+3.3V) (analog system)
23 to 26
NC
-
Not used
27
CD_DI
O
Serial data output to the digital servo processor
28
CD_CL
O
Serial data transfer clock signal output to the digital servo processor
29
CD_DO
I
Serial data input from the digital servo processor
30
CD_CE
O
Chip enable signal output to the digital servo processor
31
DVDD
-
Power supply terminal (+3.3V) (digital system)
32
DVSS
-
Ground terminal (digital system)
33 to 36
GP30 (NCO) to
GP33 (NCO)
-
Not used
37
SBSY
I
CD sub-code block sync signal input from the digital servo processor
38
SFSY
I
CD sub-code fl ame sync signal input from the digital servo processor
39
PW
I
CD sub-code PW data input from the digital servo processor
40
SBCK
I
Clock signal for CD sub-code data input from the digital servo processor
41
DVDD
-
Power supply terminal (+3.3V) (digital system)
42
DVSS
-
Ground terminal (digital system)
43
REG1_EXTR (OPN)
-
Internal regulator reserve terminal Not used
44
DVDD15
-
External capacitor connection terminal for internal regulator
45
TXD1
O
UART data output to the system controller
46
RXD1
I
UART data input from the system controller
47
SMONI
O
Watch-dog timer status monitor output to the system controller
48
OPCDM
I
External decode permission signal input from the digital servo processor
49
DVDD
-
Power supply terminal (+3.3V) (digital system)
50
DVSS
-
Ground terminal (digital system)
51
RESETB
I
Reset signal input from the system controller “L”: reset
52
SIFCK
I
Serial data transfer clock signal input from the system controller
53
SIFDI
I
Serial data input from the system controller
54
SIFDO
O
Serial data output to the system controller
55
SIFCE
I
Chip enable signal input from the system controller
56
BUSYB
O
Busy signal output to the system controller “L”: busy
57
CD_BUSYB
I
Busy signal input from the digital servo processor “L”: busy
58
LRCK
I
L/R sampling clock signal input from the digital servo processor
59
BCK
I
Bit clock signal input from the digital servo processor
60
DATA
I
Audio data input from the digital servo processor
61
MCLK
I
Master clock signal input from the digital servo processor
62
USB_IN
O
USB device detection signal output to the system controller “L”: USB device is connected
63
GP45 (NCO)
-
Not used
MAIN BOARD IC601 LC786800E-06US-H (USB CONTROLLER, INPUT SELECTOR, AUDIO DSP, ELECTRICAL VOLUME)
CDX-G3000UE/G3000UP/G3000UV/G3050UP/G3050UV/G3070UV
28
Pin No.
Pin Name
I/O
Description
64
MECHA SEL
I
CD mechanism deck detection signal input terminal “H”: CD mechanism deck is detected
Fixed at “H” in this unit
Fixed at “H” in this unit
65
GP47 (NCO)
-
Not used
66
DVSS
-
Ground terminal (digital system)
67
DVDD
-
Power supply terminal (+3.3V) (digital system)
68
UDM1
I/O
Two-way USB data (–) bus with the USB connector
69
UDP1
I/O
Two-way USB data (+) bus with the USB connector
70
DVSS
-
Ground terminal (for digital system)
71
UDM2
I/O
Two-way USB data (–) bus terminal Fixed at “L” in this unit
72
UDP2
I/O
Two-way USB data (+) bus terminal Fixed at “L” in this unit
73
XVDD
-
Power supply terminal (+3.3V) (for oscillation circuit)
74
X12IN
I
System clock input terminal (12 MHz)
75
X12OUT
O
System clock output terminal (12 MHz)
76
XVSS
-
Ground terminal (for oscillation circuit)
77
AFILT
O
Charge pump output terminal for PLL
78, 79
VVDD2, VVDD3
-
Power supply terminal (+3.3V) (for PLL)
80
DVSS
-
Ground terminal (digital system)
81
DVDD
-
Power supply terminal (+3.3V) (digital system)
82
CP_SCL
O
Serial data transfer clock signal output to the EEPROM
83
CP_SDA
I/O
Two-way data bus with the EEPROM
84
CP_RESET
O
Reset signal output terminal Not used
85
CD_RESB
I
Reset signal input from the digital servo processor “L”: reset
86
CMD_ERR
O
Command error signal output to the system controller “H”: error
87
TEST0 (GND)
I
Test mode setting terminal Fixed at “L”
88
DVDD
-
Power supply terminal (+3.3V) (digital system)
89
DVSS
-
Ground terminal (for digital system)
90
DVDD15
-
External capacitor connection terminal for internal regulator
91
JTRSTB (IPD)
I
Reset signal input terminal (for JTAG) Normally: fi xed at “L”
92
JTCK (IPD)
I
Clock signal input terminal (for JTAG) Normally: fi xed at “L”
93
JTDI (IPD)
I
Data input terminal (for JTAG) Normally: fi xed at “L”
94
JTMS (IPU)
I
Mode selection signal input terminal (for JTAG) Normally: fi xed at “H”
95
JTDO (O)
O
Data output terminal (for JTAG) Normally: open
96
JTRTCK (O)
O
Return clock signal output terminal (for JTAG) Normally: open
97
TEST1 (GND)
I
Test mode setting terminal Fixed at “L”
98
AVDD1
-
Power supply terminal (+3.3V) (analog system)
99
AVSS1
-
Ground terminal (analog system)
100
LRREF
-
External capacitor connection terminal for audio D/A converter and electrical volume reference
voltage
voltage
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