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AG10

RBA2

O

Bank address signal output to the SD-RAM

AG11, 

AG13

RA2, RA11

O

Address signal output to the SD-RAM

AG14

RDQ0

I/O

Two-way data bus with the SD-RAM

AG16

RDQS0

O

Data strobe signal (positive) output to the SD-RAM

AG17

RCLK0

O

Clock signal (positive) output to the SD-RAM

AG18

RDQS1_

O

Data strobe signal (negative) output to the SD-RAM

AG19, 

AG20

RDQ7, RDQ4

I/O

Two-way data bus with the SD-RAM

AG21 to 

AG23

NFD7, NFD4, NFD2

I/O

Two-way data bus with the NAND fl ash

AG25

GPIO8

O

VBUS on/off control signal output terminal for WLAN/BT COMBO card    “H”: VBUS on

AG26

VCLK

O

Serial data transfer clock signal output to the system controller

AG27

VDATA

I

Serial data input from the system controller

AG28

LCDRD

O

Serial data output to the system controller

AH1 to 

AH3

RDQ18, RDQ19, 

RDQ24

I/O

Two-way data bus with the SD-RAM

AH4

RDQM3

O

Data mask signal output to the SD-RAM

AH5

RDQS2_

O

Data strobe signal (negative) output to the SD-RAM

AH6

RCLK1_

O

Clock signal (negative) output to the SD-RAM

AH7

RDQS3

O

Data strobe signal (positive) output to the SD-RAM

AH8

RDQ23

I/O

Two-way data bus with the SD-RAM

AH10, 

AH11

RA0, RA7

O

Address signal output to the SD-RAM

AH13

RCKE

O

Clock enable signal output to the SD-RAM

AH14

RDQ2

I/O

Two-way data bus with the SD-RAM

AH16

RDQS0_

O

Data strobe signal (negative) output to the SD-RAM

AH17

RCLK0_

O

Clock signal (negative) output to the SD-RAM

AH18

RDQS1

O

Data strobe signal (positive) output to the SD-RAM

AH19

RDQM0

O

Data mask signal output to the SD-RAM

AH20

RDQ6

I/O

Two-way data bus with the SD-RAM

AH22, 

AH23

NFD5, NFD3

I/O

Two-way data bus with the NAND fl ash

AH25

OPWRSB

O

Power control signal output to the system controller

AH26

UATXD

-

Not used

AH27

VSTB

-

Not used

AH28

IR

-

Not used

A1

VDDQ

-

DQ Power Supply: 1.5V +/-0.075V

A2

DQU5

I/O

Data Input/output: Bi-directional data bus.

A3

DQU7

I/O

Data Input/output: Bi-directional data bus.

A4

NO_USE

-

Not used

A5

NO_USE

-

Not used

A6

NO_USE

-

Not used

A7

DQU4

I/O

Data Input/output: Bi-directional data bus.

A8

VDDQ

-

DQ Power Supply: 1.5V +/-0.075V

A9

VSS

-

Ground

B1

VSSQ

-

DQ Ground

B2

VDD

-

Power Supply: 1.5V +/-0.075

B3

VSS

-

Ground

B4

NO_USE

-

Not used

B5

NO_USE

-

Not used

B6

NO_USE

-

Not used

B7

DQSU

I/O

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with 
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling 
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only 
and does not support single-ended.

B8

DQU6

I/O

Data Input/output: Bi-directional data bus.

B9

VSSQ

-

DQ Ground

C1

VDDQ

-

DQ Power Supply: 1.5V +/-0.075V

C2

DQU3

I/O

Data Input/output: Bi-directional data bus.

C3

DQU1

I/O

Data Input/output: Bi-directional data bus.

C4

NO_USE

-

Not used

C5

NO_USE

-

Not used

C6

NO_USE

-

Not used

C7

DQSU

I/O

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with 
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling 
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only 
and does not support single-ended.

C8

DQU2

I/O

Data Input/output: Bi-directional data bus.

C9

VDDQ

-

DQ Power Supply: 1.5V +/-0.075V

D1

VSSQ

-

DQ Ground

D2

VDDQ

-

DQ Power Supply: 1.5V +/-0.075V

D3

DMU

I

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM 
is sampled HIGH coincident with that input data during a Write access. DM is sampled on 
both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode 
Register A11 setting in MR1.

D4

NO_USE

-

Not used

D5

NO_USE

-

Not used

D6

NO_USE

-

Not used

D7

DQU0

I/O

Data Input/output: Bi-directional data bus.

D8

VSSQ

-

DQ Ground

D9

VDD

-

Power Supply: 1.5V +/-0.075

E1

VSS

-

Ground

E2

VSSQ

-

DQ Ground

E3

DQL0

I/O

Data Input/output: Bi-directional data bus.

E4

NO_USE

-

Not used

E5

NO_USE

-

Not used

E6

NO_USE

-

Not used

E7

DML

I

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM 
is sampled HIGH coincident with that input data during a Write access. DM is sampled on 
both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode 
Register A11 setting in MR1.

E8

VSSQ

-

DQ Ground

E9

VDDQ

-

DQ Power Supply: 1.5V +/-0.075V

F1

VDDQ

-

DQ Power Supply: 1.5V +/-0.075V

F2

DQL2

I/O

Data Input/output: Bi-directional data bus.

F3

DQSL

I/O

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with 
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling 
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only 
and does not support single-ended.

F4

NO_USE

-

Not used

F5

NO_USE

-

Not used

F6

NO_USE

-

Not used

F7

DQL1

I/O

Data Input/output: Bi-directional data bus.

F8

DQL3

I/O

Data Input/output: Bi-directional data bus.

F9

VSSQ

-

DQ Ground

G1

VSSQ

-

DQ Ground

G2

DQL6

I/O

Data Input/output: Bi-directional data bus.

G3

DQSL

I/O

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with 
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling 
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only 
and does not support single-ended.

G4

NO_USE

-

Not used

G5

NO_USE

-

Not used

G6

NO_USE

-

Not used

G7

VDD

-

Power Supply: 1.5V +/-0.075

G8

VSS

-

Ground

G9

VSSQ

-

DQ Ground

H1

VREFDQ

-

Reference voltage for DQ

H2

VDDQ

-

DQ Power Supply: 1.5V +/-0.075V

H3

DQL4

I/O

Data Input/output: Bi-directional data bus.

H4

NO_USE

-

Not used

H5

NO_USE

-

Not used

H6

NO_USE

-

Not used

H7

DQL7

I/O

Data Input/output: Bi-directional data bus.

H8

DQL5

I/O

Data Input/output: Bi-directional data bus.

H9

VDDQ

-

DQ Power Supply: 1.5V +/-0.075V

J1

NC

-

No Connect: No internal electrical connection is present.

J2

VSS

-

Ground

J3

RAS

I

Command Input: RAS (along with CS) defi ne the command being entered.

J4

NO_USE

-

Not used

J5

NO_USE

-

Not used

J6

NO_USE

-

Not used

J7

CK

I

Clock: CK is differential clock input. All address and control input signals are sampled on the 
crossing of the positive edge of CK. Output (read) data is referenced to the crossing of CK.

J8

VSS

-

Ground

J9

NC

-

No Connect: No internal electrical connection is present.

K1

ODT

I

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the 
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, 
NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 confi gura-
tions. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT.

K2

VDD

-

Power Supply: 1.5V +/-0.075

K3

CAS

I

Command Input: CAS (along with CS) defi ne the command being entered.

K4

NO_USE

-

Not used

K5

NO_USE

-

Not used

K6

NO_USE

-

Not used

K7

CK

I

Clock: CK is differential clock input. All address and control input signals are sampled on the 
crossing of the negative edge of CK. Output (read) data is referenced to the crossing of CK.

K8

VDD

-

Power Supply: 1.5V +/-0.075

K9

CKE

I

Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signal and de-
vice input buffers and output drivers. Talking CKE LOW provides Precharge Power-Down and 
Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE 
is asynchronous for self refresh exit. After V

REFCA

 has become stable during the power on and 

initialization sequence, it must be maintained during all operations (including Self-Refresh). 
CKE must be maintained high throughout read and write accesses. Input buffers, excluding 
CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are 
disabled during Self-Refresh.

L1

NC

-

No Connect: No internal electrical connection is present.

L2

CS

I

Chip Select: All commands are masked when CS is registered HIGH. CS provides for external 
Rank selection on system with multiple Ranks. CS is considered part of the command code.

L3

WE

I

Command Input: WE (along with CS) defi ne the command being entered.

L4

NO_USE

-

Not used

L5

NO_USE

-

Not used

L6

NO_USE

-

Not used

L7

A10

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Auto-
precharge should be performed to the accessed bank after the Read/Write operation. (HIGH: 
Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine the Percharge applies to one bank 
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected 
by bank adresses.

L8

ZQ

-

Reference Pin for ZQ calibration

L9

NC

-

No Connect: No internal electrical connection is present.

M1

VSS

-

Ground

M2

BA0

I

Bank Address Inputs: BA0 defi ne to which bank an Active, Read, Write or Precharge com-
mand is being applied. Bank address also determines if the mode register or extended mode 
register is to be accessed during a MRS cycle.

M3

BA2

I

Bank Address Inputs: BA2 defi ne to which bank an Active, Read, Write or Precharge com-
mand is being applied. Bank address also determines if the mode register or extended mode 
register is to be accessed during a MRS cycle.

M4

NO_USE

-

Not used

M5

NO_USE

-

Not used

M6

NO_USE

-

Not used

M7

NC

-

No Connect: No internal electrical connection is present.

M8

VREFCA

-

Reference voltage for CA

M9

VSS

-

Ground

N1

VDD

-

Power Supply: 1.5V +/-0.075

N2

A3

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

N3

A0

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

N4

NO_USE

-

Not used

N5

NO_USE

-

Not used

N6

NO_USE

-

Not used

N7

A12

I

Address inputs: Provided the row address for active commands and the column address 
for Read/Write commands to select one location out of the memory array in the respective 
bank. The address inputs also provide the op-code during Mode Register Set commands.
Burst Chop: A12 is sampled during Read and Write commands to determine if burst chop (on-
the-fl y) will be performed. (HIGH: no burst chop, LOW: burst chopped).