Sony HBD-NF7220 Service Manual ▷ View online
HBD-NF7220
93
Pin No.
Pin Name
I/O
Description
P10
DDRVCCK
-
Power supply terminal (+1.2V)
P11 to
P18
DGND12_K
-
Ground terminal
P19, P20
DVCC12_K
-
Power supply terminal (+1.2V)
P22
VOUTCLK
-
Not used
P23 to
P26
VOUTD14,
VOUTD12,
VOUTD12,
VOUTD13, VOUTD15
-
Not used
P27
HDMI_RX_0
I
TMDS data (positive) input from the HDMI IN 1 connector
P28
HDMI_RX_0B
I
TMDS data (negative) input from the HDMI IN 1 connector
R1
RA0_B
O
Address signal output to the SD-RAM
R2
RDQ20_B
I/O
Two-way data bus with the SD-RAM
R3, R4
RA6_B, RA8_B
O
Address signal output to the SD-RAM
R5
RCAS__B
O
Column address signal output to the SD-RAM
R7
DDRVCCIO1
-
Power supply terminal (+1.5V)
R8
DGND12_K
-
Ground terminal
R10
DVCC12_K
-
Power supply terminal (+1.2V)
R11 to
R19
DGND12_K
-
Ground terminal
R20
DVCC12_K
-
Power supply terminal (+1.2V)
R22
AVSS33_HDMI_RX
-
Ground terminal
R23, R24
VOUTD8, VOUTD3
-
Not used
R25
AVDD33_HDMI_SUB
-
Power supply terminal (+3.3V)
R26
AVDD33_HDMI_RX
-
Power supply terminal (+3.3V)
R27
HDMI_RX_C
I
TMDS clock (positive) signal input from the HDMI IN 1 connector
R28
HDMI_RX_CB
I
TMDS clock (negative) signal input from the HDMI IN 1 connector
T1 to T3
RA7_B, RA2_B,
RA9_B
O
Address signal output to the SD-RAM
T4
RRESET_B
O
Reset signal output to the SD-RAM “L”: reset
T5, T6
RA4_B, RA14_B
O
Address signal output to the SD-RAM
T7
DGND12_K
-
Ground terminal
T8
DDRVCCIO1
-
Power supply terminal (+1.5V)
T10
DDRVCCK
-
Power supply terminal (+1.2V)
T11 to
T18
DGND12_K
-
Ground terminal
T19, T20
DVCC12_K
-
Power supply terminal (+1.2V)
T22
AVSS33_VDAC_BG
-
Ground terminal
T26
VOUTD10
-
Not used
T27
AVDD33_VDAC_BG
-
Power supply terminal (+3.3V)
U3 to U5
RA5_B, RA3_B,
RA11_B
O
Address signal output to the SD-RAM
U6
RBA1_B
O
Bank address signal output to the SD-RAM
U7
DDRVCCIO1
-
Power supply terminal (+1.5V)
U8
DGND12_K
-
Ground terminal
U10
DVCC12_K
-
Power supply terminal (+1.2V)
U12 to
U19
DGND12_K
-
Ground terminal
U20
DVCC12_K
-
Power supply terminal (+1.2V)
U21
DVCC33_IO_4
-
Power supply terminal (+3.3V)
U22
AVSS33_VDAC_X
-
Ground terminal
U23 to
U26
VOUTD9, VOUTD7,
VOUTD6, VOUTD11
-
Not used
U27
VDACX_OUT
-
Not used
U28
VDACB_OUT
-
Not used
V1
RRAS__B
O
Row address signal output to the SD-RAM
V2
RCKE_B
O
Clock enable signal output to the SD-RAM
V3
RCS__B
O
Chip select signal output to the SD-RAM
V4
RCSX__B
-
Not used
HBD-NF7220
94
Pin No.
Pin Name
I/O
Description
V5, V6
RA1_B, RA12_B
O
Address signal output to the SD-RAM
V7
DGND12_K
-
Ground terminal
V8
DDRVREF_B
I
Reference voltage (+0.75V) input terminal for SD-RAM
V10
DGND12_K
-
Ground terminal
V11
DVCC12_K
-
Power supply terminal (+1.2V)
V12 to
V17
DGND12_K
-
Ground terminal
V18
DVCC12_K
-
Power supply terminal (+1.2V)
V19
DGND12_K
-
Ground terminal
V20
DVCC12_K
-
Power supply terminal (+1.2V)
V21
DVCC33_IO_4
-
Power supply terminal (+3.3V)
V22
AVDD33_VDAC_X
-
Power supply terminal (+3.3V)
V23 to
V25
VOUTD2, VOUTD4,
VOUTD5
-
Not used
V28
VDACG_OUT
-
Not used
W1, W2
RDQ0_B, RDQ2_B
I/O
Two-way data bus with the SD-RAM
W3
DDRVCCIO1
-
Power supply terminal (+1.5V)
W4, W5
RDQ8_B, RDQ9_B
I/O
Two-way data bus with the SD-RAM
W6
RA10_B
O
Address signal output to the SD-RAM
W8
DDRVCCIO1
-
Power supply terminal (+1.5V)
W10
DDRVCCK
-
Power supply terminal (+1.2V)
W11,
W12
DVCC12_K
-
Power supply terminal (+1.2V)
W13,
W14
DDRVCCK
-
Power supply terminal (+1.2V)
W15,
W16,
W18,
W16,
W18,
W19
DVCC12_K
-
Power supply terminal (+1.2V)
W20
DGND12_K
-
Ground terminal
W25,
W26
VOUTD1, VOUTD0
-
Not used
W27
VDACR_OUT
-
Not used
W28
USB_VRT_P2
-
External reference resistor connection terminal
Y3, Y4
RDQ1_B, RDQ10_B
I/O
Two-way data bus with the SD-RAM
Y7
DDRVCCIO1
-
Power supply terminal (+1.5V)
Y18
DGND12_K
-
Ground terminal
Y20
AVSS33_COM
-
Ground terminal
Y22
AVSS33_USB_POP1
-
Ground terminal
Y23
DGND12_K
-
Ground terminal
Y26
AVDD33_USB_P2
-
Power supply terminal (+3.3V)
AA1
RDQS0__B
O
Data strobe signal (negative) output to the SD-RAM
AA2
RDQS0_B
O
Data strobe signal (positive) output to the SD-RAM
AA3,
AA4
RDQ3_B, RDQ11_B
I/O
Two-way data bus with the SD-RAM
AA5
RDQM1_B
O
Data mask signal output to the SD-RAM
AA6
RDQ15_B
I/O
Two-way data bus with the SD-RAM
AA7
DGND12_K
-
Ground terminal
AA15
DDRVREF_D
I
Reference voltage (+0.75V) input terminal for SD-RAM
AA17
DDRVCCIO1
-
Power supply terminal (+1.5V)
AA18
DGND12_K
-
Ground terminal
AA22
AVSS33_LD
-
Ground terminal
AA24
AVDD33_LD
-
Power supply terminal (+3.3V)
AA25
AVDD33_COM
-
Power supply terminal (+3.3V)
AA27
USB_DP_P2
I/O
Two-way USB serial data (+) with the WLAN/BT COMBO card
AA28
USB_DM_P2
I/O
Two-way USB serial data (–) with the WLAN/BT COMBO card
AB1
RCLK0__B
O
Clock signal (negative) output to the SD-RAM
AB2
RCLK0_B
O
Clock signal (positive) output to the SD-RAM
HBD-NF7220
95
Pin No.
Pin Name
I/O
Description
AB3
DDRVCCIO1
-
Power supply terminal (+1.5V)
AB4 to
AB6
RDQ12_B, RDQ14_B,
RDQ13_B
I/O
Two-way data bus with the SD-RAM
AB8,
AB9
DGND12_K
-
Ground terminal
AB11
DDRVCCIO1
-
Power supply terminal (+1.5V)
AB12
DGND12_K
-
Ground terminal
AB13
DDRVCCIO1
-
Power supply terminal (+1.5V)
AB14,
AB15
DGND12_K
-
Ground terminal
AB17
DDRVCCIO1
-
Power supply terminal (+1.5V)
AB18,
AB19
DGND12_K
-
Ground terminal
AB20
AVSS33_LDO
-
Ground terminal
AB21
AVDD12_LDO
-
Not used
AB23
MDIO
-
Not used
AB24
CEC
-
Not used
AB25
HDMISCK
I/O
Two-way I2C clock bus with the HDMI ARC OUT connector
AB26
HDMISD
I/O
Two-way I2C data bus with the HDMI ARC OUT connector
AB27
TXVN_0
O
Transmit data (negative) output to the ethernet connector
AB28
TXVP_0
O
Transmit data (positive) output to the ethernet connector
AC1
RDQS1_B
O
Data strobe signal (positive) output to the SD-RAM
AC2
RDQS1__B
O
Data strobe signal (negative) output to the SD-RAM
AC3
DDRVCCIO1
-
Power supply terminal (+1.5V)
AC4
DGND12_K
-
Ground terminal
AC5
AVDD33_MEMPLL
-
Power supply terminal (+3.3V)
AC7
DDRVREF_C
I
Reference voltage (+0.75V) input terminal for SD-RAM
AC8
RDQM2
O
Data mask signal output to the SD-RAM
AC9
DGND12_K
-
Ground terminal
AC10
RBA0
O
Bank address signal output to the SD-RAM
AC11
DDRVCCIO1
-
Power supply terminal (+1.5V)
AC12
RA6
O
Address signal output to the SD-RAM
AC14
DDRVCCIO1
-
Power supply terminal (+1.5V)
AC15
RBA1
O
Bank address signal output to the SD-RAM
AC17,
AC18
RDQ10, RDQ15
I/O
Two-way data bus with the SD-RAM
AC19
DDRVCCIO1
-
Power supply terminal (+1.5V)
AC21
NFRBN2
-
Not used
AC24
GPIO27
O
WOL (wake-on-LAN) wake-up signal output to the system controller “H”: wake-up
AC25
DDC_SCL_RX2
O
I2C clock signal output to the HDMI IN 2 connector
AC26
CEC2
-
Not used
AC27
TXVN_1
I
Receive data (negative) input from the ethernet connector
AC28
TXVP_1
I
Receive data (positive) input from the ethernet connector
AD1
RDQM0_B
O
Data mask signal output to the SD-RAM
AD2,
AD3
RDQ6_B, RDQ7_B
I/O
Two-way data bus with the SD-RAM
AD4
AVSS33_MEMPLL
-
Ground terminal
AD8
RA13
O
Address signal output to the SD-RAM
AD9
RRESET
O
Reset signal output to the SD-RAM “L”: reset
AD10
RCAS_
O
Column address signal output to the SD-RAM
AD11 to
AD15
RA14, RA8, RA1,
RA10, RA12
O
Address signal output to the SD-RAM
AD16 to
AD18
RDQ8, RDQ12,
RDQ14
I/O
Two-way data bus with the SD-RAM
AD19
DDRVCCIO1
-
Power supply terminal (+1.5V)
AD20
AVDD33_LDO
-
Power supply terminal (+3.3V)
AD21
NFRBN
O
Ready/busy selection signal output to the NAND fl ash “L”: busy, “H”: ready
AD22
NFCLE
O
Command latch enable signal output to the NAND fl ash
HBD-NF7220
96
Pin No.
Pin Name
I/O
Description
AD23
MDC
-
Not used
AD24
DDC_SDA_RX2
I/O
Two-way I2C data bus with the HDMI IN 2 connector
AD25
PWR5V_RX
I
Power supply voltage (+5V) input from the HDMI IN 1 connector
AD26
HTPLG_RX_2
O
Hot plug detection signal output to the HDMI IN 2 connector
AD27
REXT
-
External reference resistor connection terminal
AD28
HTPLG
I
Hot plug detection signal input from the HDMI ARC OUT connector
AE3
RDQ4_B
I/O
Two-way data bus with the SD-RAM
AE5
DDRVCCIO1
-
Power supply terminal (+1.5V)
AE6 to
AE8
RDQ29, RDQ31,
RDQ30
I/O
Two-way data bus with the SD-RAM
AE9
RWE_
O
Write enable signal output to the SD-RAM
AE10
RODT
O
On die termination enable signal output to the SD-RAM
AE11
RRAS_
O
Row address signal output to the SD-RAM
AE12
RA3
O
Address signal output to the SD-RAM
AE13
RCSX_
-
Not used
AE14
RA4
O
Address signal output to the SD-RAM
AE16
RDQ11
I/O
Two-way data bus with the SD-RAM
AE17
RDQM1
O
Data mask signal output to the SD-RAM
AE18
RDQ13
I/O
Two-way data bus with the SD-RAM
AE19,
AE20
DVCC33_IO_STB
-
Power supply terminal (+3.3V)
AE21
NFREN
O
Read enable signal output to the NAND fl ash
AE22
NFCEN2
-
Not used
AE23
NFD0
I/O
Two-way data bus with the NAND fl ash
AE24
NFWEN
O
Write enable signal output to the NAND fl ash
AE25
HTPLG_RX
O
Hot plug detection signal output to the HDMI IN 1 connector
AE26
PWR5V_RX2
I
Power supply voltage (+5V) input from the HDMI IN 2 connector
AF1, AF2
TP_MEM_PLL,
TN_MEMPLL
-
Not used
AF3
RDQ5_B
I/O
Two-way data bus with the SD-RAM
AF4
RDQ25
I/O
Two-way data bus with the SD-RAM
AF5
DGND12_K
-
Ground terminal
AF6
RDQ28
I/O
Two-way data bus with the SD-RAM
AF7
DDRVCCIO1
-
Power supply terminal (+1.5V)
AF8, AF9
RDQ20, RDQ22
I/O
Two-way data bus with the SD-RAM
AF10
DDRVCCIO1
-
Power supply terminal (+1.5V)
AF11,
AF12
RA9, RA5
O
Address signal output to the SD-RAM
AF13
RCS_
O
Chip select signal output to the SD-RAM
AF14 to
AF16
RDQ3, RDQ1, RDQ9
I/O
Two-way data bus with the SD-RAM
AF17,
AF18
DDRVCCIO1
-
Power supply terminal (+1.5V)
AF20
RDQ5
I/O
Two-way data bus with the SD-RAM
AF21
NFD6
I/O
Two-way data bus with the NAND fl ash
AF22
NFCEN
O
Chip enable signal output to the NAND fl ash
AF23
NFD1
I/O
Two-way data bus with the NAND fl ash
AF24
NFALE
O
Address latch enable signal output to the NAND fl ash
AF25
UARXD
-
Not used
AF26
RESET_
I
Reset signal input from the system controller “L”: reset
AF27
DDC_SDA_RX
I/O
Two-way I2C data bus with the HDMI IN 1 connector
AF28
DDC_SCL_RX
O
I2C clock signal output to the HDMI IN 1 connector
AG1 to
AG4
RDQ17, RDQ16,
RDQ26, RDQ27
I/O
Two-way data bus with the SD-RAM
AG5
RDQS2
O
Data strobe signal (positive) output to the SD-RAM
AG6
RCLK1
O
Clock signal (positive) output to the SD-RAM
AG7
RDQS3_
O
Data strobe signal (negative) output to the SD-RAM
AG8
RDQ21
I/O
Two-way data bus with the SD-RAM
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