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N8

BA1

I

Bank Address Inputs: BA1 defi ne to which bank an Active, Read, Write or Precharge com-
mand is being applied. Bank address also determines if the mode register or extended mode 
register is to be accessed during a MRS cycle.

N9

VDD

-

Power Supply: 1.5V +/-0.075

P1

VSS

-

Ground

P2

A5

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

P3

A2

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

P4

NO_USE

-

Not used

P5

NO_USE

-

Not used

P6

NO_USE

-

Not used

P7

A1

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

P8

A4

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

P9

VSS

-

Ground

R1

VDD

-

Power Supply: 1.5V +/-0.075

R2

A7

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

R3

A9

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

R4

NO_USE

-

Not used

R5

NO_USE

-

Not used

R6

NO_USE

-

Not used

R7

A11

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

R8

A6

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

R9

VDD

-

Power Supply: 1.5V +/-0.075

T1

VSS

-

Ground

T2

RESET

I

Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when 
RESET is HIGH. RESET must be HIGH during normal operation. RESET is CMOS rail to rail 
signal with DC high and low at 80% and 20% of V

DD

, example, 1.20V for DC high and 0.30V 

for DC low.

T3

A13

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

T4

NO_USE

-

Not used

T5

NO_USE

-

Not used

T6

NO_USE

-

Not used

T7

NC

-

No Connect: No internal electrical connection is present.

T8

A8

I

Address inputs: Provided the row address for active commands and the column address for 
Read/Write commands to select one location out of the memory array in the respective bank. 
The address inputs also provide the op-code during Mode Register Set commands.

T9

VSS

-

Ground

1

SIRCS_IN

I

SIRCS signal input from the remote control receiver

2

FAN_CONT

O

Fan motor control signal output terminal 

3

FL_DOUT

O

Serial data output to the fl uorescent indicator tube driver

4

PCONT_TS

O

Power supply on/off control signal output to the TOUCH-F & TOUCH-S board for touch sensor 
“H”: power on

5

FL_CLK

O

Serial data transfer clock signal output to the fl uorescent indicator tube 

6

BYTE

I

External data bus width selection signal input terminal

7

CNVSS

I

Processor mode slection signal input terminal

8

NFC_SW

O

Standby control signal output to the NFC

9

NFC_IRQ

I

Wireless data receive signal input from the NFC

10

RESET

I

System reset signal input terminal   “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”

11

XOUT

O

System clock output terminal (8MHz)

12

VSS

-

Ground terminal

13

XIN

I

System clock input terminal (8MHz)

14

VCC1

-

Power supply terminal (+3.3V)

15

CEC_TX_RX

I/O

CEC serial data input/output with the HDMI connector

16

TS_INT

I

Touch sensor detection signal input from the TOUCH-F & TOUCH-S board 
“L”: touch sensor is detected

17

NO_USE

-

Not used

18

AC_CUT

I

AC cut detection signal input terminal   “L”: AC cut

19

BD_IF_START

O

Ready signal output to the BD decoder  “H”: ready

20

LED_PWM3

O

LED drive signal output terminal for power on indicator   “H”: LED on

21

TS_RST

O

Touch sensor reset signal output to the TOUCH-F &TOUCH-S board   “L”: reset

22

BT_LED

O

LED drive signal output terminal for Bluetooth status indicator   “H”: LED on

23

BD_IF_REQ

I

Request signal input from the BD decoder   “H”: request

24

LED_PWM2

O

LED drive signal output to the TOUCH-F & TOUCH-S board for touch sensor back light   
“H”: LED on

25

PCONT_FL

O

Power supply on/off control signal output terminal for fl uorescent indicator tube  
“H”: power on

26

LED_PWM 1

O

LED drive signal output to the TOUCH-F & TOUCH-S board for touch sensor back light   
“H”: LED on

27

WS_SCL

I/O

Two-way I2C clock bus with the RF modulator

28

WS_SDA

I/O

Two-way I2C data bus with the RF modulator

29

TxD1

O

Transmit data output terminal

30

RxD1

I

Receive data input teminal

31

ON_CHIP_DEBUG / 

CLK1

I

On chip debuger / fl ash write CLK1

32

NO_USE / RTS1

O

Not used / fl ash write RTS1

33

DAMP_SDA

I/O

Two-way I2C data bus with the DAMP processor

34

DAMP_SCL

I/O

Two-way I2C clock bus with the DAMP processor

35

DC_DET

I

Speaker DC detection signal input terminal   “L”: speaker DC is detected 

36 to 38

PCONT1 to PCONT3

O

Power supply on/off control signal output terminal   “H”: power on 

39

EPM

O

EPM signal output terminal

40

PCONT_PVDD

O

Power control for PVDD

41

NO_USE

-

Not used

42

FAN_ON

O

Power supply on/off control signal output terminal for fan motor   “H”: power on

43

LED_DRV_DATA

I/O

Two-way I2C data bus with the LED driver

44

CE

I

Chip enable signal input terminal

45

ST_SDA

I/O

Two-way I2C data bus with the FM receiver

46

ST_SCL

I/O

Two-way I2C clock bus with the FM receiver

47

PVDD_VOL_SEL

O

PVDD voltage selection signal output to the switching regulator

48

DAMP_XPDN

O

Power down signal output to the power amplifi er   “L”: power down

49

NO_USE

-

No used

50

DRIVER_XPDN

O

DAMP driver power down control

51

DAMP_XRST

O

Reset signal output to the DAMP processor  “L”: reset

52

DAMP_XMUTE

O

Muting on/off control signal output to the DAMP processor  “L”: muting on

53

LED_DRV_CLK

I/O

Two-way I2C clock bus with the LED driver

54

TS_SDA

I/O

Two-way I2C data bus with the TOUCH-F & TOUCH-S board

55

TS_SCL

I/O

Two-way I2C clock bus with the TOUCH-F & TOUCH-S board

56

PCONT_WOL_

STANDBY

O

Power supply on/off control signal output terminal   “H”: power on

57

NO_USE

-

Not used

58

S-AIR_INT

I

Wireless sound interrupt

59

LED_DRV_POWER

O

LED driver reset control

60

VCC2

-

Power supply terminal (+3.3V)

61

NO_USE

-

Not used

62

VSS

-

Ground terminal

63

PLUG DET 

I

Calibration microphone plug insert detection signal input terminal
“H”: microphone plug is inserted

64

NO_USE

-

Not used

65

DRIVE_SD /

POWER_DET

I

Shut down signal input from the power amplifi er   “L”: shut down

66

NO_USE

-

Not used

67

DRIVER_TH_WARN

I

Thermal warning detection signal input from the power amplifi er   “L”: thermal warning

68

FL_CS

O

Chip select signal output to the fl uorescent indicator tube 

69

ASEL0

O

Audio selection signal output terminal  

70

ASEL1

O

Audio selection signal output terminal   

71

WOL_WLAN

I

WOL (wake-on-LAN) wake-up signal input from the BD decoder   “H”: wake-up

72

NFC_RFDET

I

RF detection signal input from the NFC

73

ST_RDS_INT

I

RDS interrupt signal input from the FM receiver

74

NAND_RESET

O

Reset signal output to the NAND fl ash   “L”: reset

75

BD_SDI (IF_SDO)

O

Serial data output to the BD decoder

76

BD_SDO (IF_SDI)

I

Serial data input from the BD decoder

77

BD_CLK

I

Serial data transfer clock signal input from the BD decoder

78

BD_CS

O

Chip select signal output to the BD decoder

79

NFC_DATA

I/O

Two-way data bus with the NFC

80

NFC_SPICLK

O

Serial data transfer clock signal output to the NFC

81

BD_RESET

O

Reset signal output to the BD decode   “L”: reset

82

JIG_MODE1

I/O

Jig mode selection signal input from the BD decoder

83

OPWRSB

I

Power control signal input from the BD decoder

84

FE_EJECT

-

Not used

85

UPG STATUS

I

UPG status signal input from the BD decoder

86

S-AIR_RST

O

Reset signal output to the RF modulator   “L”: reset

87

NO_USE

-

Not used

88

NO_USE

-

Not used

89

KEY0

I

Front panel key input terminal

90

NO_USE

-

Not used

91

MODEL

I

Model setting terminal   Fixed at “H” in this unit

92

NO_USE

-

Not used

93

NO_USE

-

Not used

94

AVSS

-

Ground terminal

95

BD_TEMP

-

Not used

96

VREF

I

Reference voltage (+3.3V) input terminal

97

AVCC

-

Power supply terminal (+3.3V)

98

NFC_SEL

O

Data read/write control signal output to the NFC

99

VACS_FAST

-

Not used

100

DESTINATION

I

Destination setting terminal   Fixed at “L” in this unit

Note:
•  -XX and -X mean standardized parts, so 

they may have some difference from the 
original one.

•  Items marked “*” are not stocked since 

they are seldom required for routine ser-
vice. Some delay should be anticipated 
when ordering these items.

•  The mechanical parts with no reference 

number in the exploded views are not sup-
plied.

•  Color Indication of Appearance Parts Ex-

ample:

  KNOB, BALANCE (WHITE) . . . (RED)
   

 

 



   

 

Parts Color  Cabinet’s Color

The components identifi ed by mark 

0 

or dotted line with mark 

0 are critical for 

safety.
Replace only with part number specifi ed.

The components identifi ed by mark 

9 con-

tain confi dential information.
Strictly follow the instructions whenever the 
components are repaired and/or replaced.

 1 

4-461-057-01 PLATE 

(BD-H)

 2 

4-674-137-11 SCREW 

(PTP2X5)

 3 

X-2589-389-1 COVER 

(TOP) 

ASSY

  Ref. No. 

Part No. 

Description 

Remark