DOWNLOAD Sharp LC-37RD2E (serv.man6) Service Manual ↓ Size: 1.52 MB | Pages: 30 in PDF or view online for FREE

Model
LC-37RD2E (serv.man6)
Pages
30
Size
1.52 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Major IC Informations
File
lc-37rd2e-sm6.pdf
Date
PREV: Sharp LC-37RD2E (serv.man5) Service Manual

Sharp LC-37RD2E (serv.man6) Service Manual ▷ View online

LC-32RD2E/RU, LC-37RD2E/RU
6 – 17
189
VIN3
I
Analog Video 3 CVBS Input
190
VIN2
I
Analog Video 2 CVBS Input
191
VIN1
I
Analog Video 1 CVBS Input
192
VSUP3.3VO
—
Supply Voltage Analog Video Output, 3.3 V
193
VOUT3
O
Analog CVBS Video 3 Output
194
VOUT2
O
Analog CVBS Video 2 Output
195
VOUT1
O
Analog CVBS Video 1 Output
196
GND3.3IO3
—
Ground Digital Input/Output Port 1
197
VSUP3.3IO3
—
Supply Voltage Input/Output Port 1, 3.3 V
198
656I0 P3_0
I
DTM_IRQI (Interrupt from DTV)
199
656I1 P3_1
I
AVLINK_1 (AVLINK (BL_ERR))
200
656I2 P3_2
I
AVLINK_2 (AVLINK (POW_ERR))
201
656I3 P3_3
I
HDMI_INT_I (Interrupt from Receiver)
202
656I4 P3_4
I
HDMI_INT_I (Interrupt from Receiver)
203
656I5 P3_5
I
HOTP_CONT0 (HDMI Insertion/Removal Detection)
204
656I6 P3_6
I
MIC_IREQ (Interrupt from Microprocessor)
205
656I7 P3_7
I
HOTP_CONT1 (HDMI Insertion/Removal Detection)
206
656CLKI
I
Digital 656 Clock Input
207
656CLKO
O
Digital 656 Clock Output
208
P4_7
I
RXD (Not used)
Pin No.
Pin Name
I/O
Pin Function
LC-32RD2E/RU, LC-37RD2E/RU
6 – 18
2.9. IC3301 (RH-iXB922WJZZQ)
2.9.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
General pins
C2
XIN
I
20.25MHz clock or crystal input
C1
XOUT
O
Output to a crystal that is connected to XIN. If crystal is not used, leave pin open
U10
RESET_N
I
Reset Input (active low). A reset pulse should be applied immediately after power-on 
for proper operation for a minimum of 1.3 
µs (tbd)
M16
TM
I
Test Mode Enable
T10
RX
I
Receiver (UART)
V10
TX
O
Transmitter (UART)
T9
GPIO
I/O
General CPU purpose I/O (under discussion, only output for data sheet)
DDR-SDRAM Interface pins
U6
RAMDQ15
I/O
DRAM bidirectional data bus
T6
RAMDQ14
I/O
V7
RAMDQ13
I/O
U7
RAMDQ12
I/O
T7
RAMDQ11
I/O
V8
RAMDQ10
I/O
U8
RAMDQ9
I/O
T8
RAMDQ8
I/O
N3
RAMDQ7
I/O
P1
RAMDQ6
I/O
P2
RAMDQ5
I/O
P3
RAMDQ4
I/O
R1
RAMDQ3
I/O
R2
RAMDQ2
I/O
R3
RAMDQ1
I/O
T1
RAMDQ0
I/O
T5
RAMA11
O
Address bits for DRAM (Column/Row)
T2
RAMA10
O
T4
RAMA9
O
U4
RAMA8
O
V4
RAMA7
O
U3
RAMA6
O
V3
RAMA5
O
V2
RAMA4
O
V1
RAMA3
O
U2
RAMA2
O
U1
RAMA1
O
T3
RAMA0
O
L2
RAMBA1
O
DRAM bank address
L3
RAMBA0
O
M2
RAMRAS_N
O
DRAM row address strobe (active low)
M3
RAMCAS_N
O
DRAM column address strobe (active low)
N1
RAMWE_N
O
DRAM write enable (active low)
M1
RAMCS_N
O
DRAM chip select (active low)
U9
RAMCLKE
O
DRAM clock enable
U5
RAMCLK
O
DRAM clock output
V6
RAMCLK_N
O
DRAM complementary clock signal
V9
RAMUDQS
I/O
DRAM Strobe upper byte
N2
RAMLDQS
I/O
DRAM Strobe lower byte
V5
RAMCLKIN
I
Clock (RAM2CLK) feedback
I2C Bus pins
L1
SCL
I/O
I2C Bus 1 Clock
K2
SDA
I/O
I2C Bus 1 Data
JTAG Interface pins
B1
TMS
I
JTAG Interface mode select input
A1
TDI
I
JTAG Interface data input
B2
TDO
O
JTAG Interface data output
A2
TCLK
I
JTAG Interface clock
B3
TRST
I
JTAG Interface reset
L C - 3 2 R D 2 E /R U ,  L C - 3 7 R D 2 E /R U
6 – 19
Pin No.
Pin Name
I/O
Pin Function
Port A pins
C13
PORT_A_VA
I
Port A control
A13
PORT_A_HA
I
B14
PORT_A_DEA
I
C3
PORT_A_CLKA1
I
Port A clk1
A3
PORT_A_CLKA2
I
Port A clk2
B7
PORT_A_A29
I
Port A data
A6
PORT_A_A28
I
C6
PORT_A_A27
I
B6
PORT_A_A26
I
A5
PORT_A_A25
I
C5
PORT_A_A24
I
B5
PORT_A_A23
I
A4
PORT_A_A22
I
C4
PORT_A_A21
I
B4
PORT_A_A20
I
B10
PORT_A_A19
I
A9
PORT_A_A18
I
C9
PORT_A_A17
I
B9
PORT_A_A16
I
D9
PORT_A_A15
I
A8
PORT_A_A14
I
C8
PORT_A_A13
I
B8
PORT_A_A12
I
A7
PORT_A_A11
I
C7
PORT_A_A10
I
B13
PORT_A_A9
I
A12
PORT_A_A8
I
C12
PORT_A_A7
I
B12
PORT_A_A6
I
A11
PORT_A_A5
I
C11
PORT_A_A4
I
B11
PORT_A_A3
I
D11
PORT_A_A2
I
A10
PORT_A_A1
I
C10
PORT_A_A0
I
Port B pins
F1
PORT_B_B15
I
Port B data
F3
PORT_B_B14
I
F2
PORT_B_B13
I
G1
PORT_B_B12
I
G3
PORT_B_B11
I
G2
PORT_B_B10
I
G4
PORT_B_B9
I
H1
PORT_B_B8
I
H3
PORT_B_B7
I
H2
PORT_B_B6
I
J1
PORT_B_B5
I
J3
PORT_B_B4
I
J2
PORT_B_B3
I
J4
PORT_B_B2
I
K1
PORT_B_B1
I
K3
PORT_B_B0
I
E2
PORT_B_VB
O
Port B control, can be set to tristate by I2C bus register SETPDPB
E3
PORT_B_HB
O
E1
PORT_B_FB
I
D3
PORT_B_HC1
I
D2
PORT_B_HC0
I
D1
PORT_B_CLKB
O
Port B clk, can be set to tristate by I2C bus register SETPDPB
LC-32RD2E/RU, LC-37RD2E/RU
6 – 20
Pin No.
Pin Name
I/O
Pin Function
Port C pins
M17
PORT_C_C29
O
Port C data, can be set to tristate by I2C bus register SETTSPCD
L18
PORT_C_C28
O
L16
PORT_C_C27
O
L17
PORT_C_C26
O
L15
PORT_C_C25
O
K18
PORT_C_C24
O
K16
PORT_C_C23
O
K17
PORT_C_C22
O
J18
PORT_C_C21
O
J16
PORT_C_C20
O
J17
PORT_C_C19
O
H18
PORT_C_C18
O
H16
PORT_C_C17
O
H17
PORT_C_C16
O
H15
PORT_C_C15
O
G18
PORT_C_C14
O
G16
PORT_C_C13
O
G17
PORT_C_C12
O
F18
PORT_C_C11
O
F16
PORT_C_C10
O
F17
PORT_C_C9
O
E18
PORT_C_C8
O
E16
PORT_C_C7
O
E17
PORT_C_C6
O
D18
PORT_C_C5
O
D16
PORT_C_C4
O
D17
PORT_C_C3
O
C18
PORT_C_C2
O
C16
PORT_C_C1
O
C17
PORT_C_C0
O
B18
PORT_C_PCS3
O
Port C control, can be set to tristate by I2C bus register SETTSPCC
B17
PORT_C_PCS2
O
A18
PORT_C_PCS1
O
A17
PORT_C_CLKC
O
Port C clk, can be set to tristate by I2C bus register SETTSPCC
Port D pins
T12
PORT_D_D29
O
Port D data, can be set to tristate by I2C bus register SETTSPDD
U12
PORT_D_D28
O
V13
PORT_D_D27
O
T13
PORT_D_D26
O
U13
PORT_D_D25
O
V14
PORT_D_D24
O
T14
PORT_D_D23
O
U14
PORT_D_D22
O
V15
PORT_D_D21
O
T15
PORT_D_D20
O
U15
PORT_D_D19
O
V16
PORT_D_D18
O
T16
PORT_D_D17
O
U16
PORT_D_D16
O
V17
PORT_D_D15
O
U17
PORT_D_D14
O
V18
PORT_D_D13
O
U18
PORT_D_D12
O
T18
PORT_D_D11
O
T17
PORT_D_D10
O
R18
PORT_D_D9
O
R16
PORT_D_D8
O
R17
PORT_D_D7
O
P18
PORT_D_D6
O
P16
PORT_D_D5
O
P17
PORT_D_D4
O
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