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LC-32RD2E/RU, LC-37RD2E/RU

6 – 21

N18

PORT_D_D3

O

Port D data, can be set to tristate by I2C bus register SETTSPDD

N16

PORT_D_D2

O

N17

PORT_D_D1

O

M18

PORT_D_D0

O

V12

PORT_D_PCS4

O

Port D control, can be set to tristate by I2C bus register SETTSPDC

U11

PORT_D_PCS5

O

T11

PORT_D_PCS6

O

V11

PORT_D_CLKD

O

Port D clk, can be set to tristate by I2C bus register SETTSPDC

Port C & D General pins
C14

PORT_C_REV

O

REV, can be set to tristate by I2C bus register SETTSPWC

C15

PORT_C_PWM3

O

PWM3, can be set to tristate by I2C bus register SETTSPWC

B15

PORT_C_PWM2

O

PWM2, can be set to tristate by I2C bus register SETTSPWC

A14

PORT_C_PWM1

O

PWM1, can be set to tristate by I2C bus register SETTSPWC

A15

PORT_C_HC

O

Horizontal Sync, can be set to tristate by I2C bus register SETTSGEC

B16

PORT_C_VC

O

Vertical Sync, can be set to tristate by I2C bus register SETTSGEC

A16

PORT_C_BLANKC

O

Blank Signal, can be set to tristate by I2C bus register SETTSGEC

Power Supply Pins
E4

VDDP_PLL

—

PLL supply power (1.05V)

D8, G15, K15, R14, 
E15, N15, R12, R10, 
D4, D6, D12, D14

VDDP

—

Pad supply power (2.5V)

G7-12, H7, H12, J7, 
J12, K7, K12, L7, 
L12, M7-12

VDD

—

Core supply power (1.05V)

N4, R9, K4, R4

VDDP_SSTL

—

DRAM interface supply power (2.6V)

Vss Pins
R8

FUSE_PWR

—

set to VSS

F4

VSS_PLL

—

PLL supply power (0V)

J15, F15, P15, R11, 
D15, M15, R15, R13, 
D5, D7, D10, D13

VSSP

—

Pad supply power (0V)

H8, H9, H10, H11, J8, 
J9, J10, J11, K8, K9, 
K10, K11, L8, L9, 
L10, L11

VSS

—

Core supply power (0V)

L4, P4, R5, R6, R7

VSSP_SSTL

—

DRAM interface supply power (0V)

LC-32RD2E/RU, LC-37RD2E/RU

6 – 22

45, 46

CK

I

Clock: CK and /CK are differential clock inputs. All address and control input signals are sam-
pled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is 
referenced to the crossings of CK and /CK (both directions of crossing).

46

/CK

I

44

CKE

I

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and 
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER 
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row 
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF 
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE 
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, 
/CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled 
during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after 
VDD is applied.

24

/CS

I

Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM.
All commands are masked when Chip Select is registered high.
Chip Select provides for external bank selection on systems with multiple banks.
Chip Select is considered part of the command code.

26

BA0

I

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.

27

BA1

I

29

A0

I

Address Inputs: Provide the row address for ACTIVE commands, and the column address and 
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory 
array in the respective bank. A10 is sampled during a precharge command to determine 
whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1.
The address inputs also provide the op code during a MODE REGISTER SET command.
BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET com-
mand (MRS or EMRS).

30

A1

I

31

A2

I

32

A3

I

35

A4

I

36

A5

I

37

A6

I

38

A7

I

39

A8

I

40

A9

I

28

A10

I

LC-32RD2E/RU, LC-37RD2E/RU

6 – 23

41

A11

I

Address Inputs: Provide the row address for ACTIVE commands, and the column address and 
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory 
array in the respective bank. A10 is sampled during a precharge command to determine 
whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1.
The address inputs also provide the op code during a MODE REGISTER SET command.
BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET com-
mand (MRS or EMRS).

23

/RAS

I

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered.

22

/CAS

I

21

/WE

I

20

LDM

I

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is 
sampled HIGH along with that input data during a WRITE access.
DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading 
matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM 
corresponds to the data on DQ8-Q15.

47

UDM

I

16

LDQS

I/O

Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered 
in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-
Q7; UDQS corresponds to the data on DQ8-Q15.

51

UDQS

2

DQ0

I/O

Data input / output pin: Data bus

4

DQ1

I/O

5

DQ2

I/O

7

DQ3

I/O

8

DQ4

I/O

10

DQ5

I/O

11

DQ6

I/O

13

DQ7

I/O

54

DQ8

I/O

56

DQ9

I/O

57

DQ10

I/O

59

DQ11

I/O

60

DQ12

I/O

62

DQ13

I/O

63

DQ14

I/O

65

DQ15

I/O

1, 15, 33/34, 48, 66

VDD/VSS

—

Power supply for internal circuits and input buffers.

3, 9, 15, 55, 61/5, 
12, 52, 58, 64

VDDQ/VSSQ

—

Power supply for output buffers for noise immunity.

49

VREF

—

Reference voltage for inputs for SSTL interface.

14, 17, 19, 25, 42, 
43, 50, 53, 

NC

—

No connection.

LC-32RD2E/RU, LC-37RD2E/RU

6 – 24

Digital power-supply ball assignment
A8, B8, B19, B20, C8, 
D8, F1, F2, F3, F4, U23, 
U24, V1, V2, V3, V4, 
AA23, AA24, AA25, 
AA26, AC7, AC15, AD7, 
AD15, AE7, AE15, AF7, 
AF15

VDD

—

1.6 V power supply.

B22, C3, C4, C10, D3, 
D4, D10, E4, G25, M1, 
M2, M3, M4, W23, W24, 
AC3, AC4, AC10, AC13, 
AC19, AC23, AC24, AD3, 
AD4, AD10, AD13, AD19, 
AD23, AD24

VDD3

—

3.3 V power supply.

AD6

RTCVDD

—

Low power controller 1.8 V power supply.

B13, B21, D25, K10 to 
K17, L10, L11, L12, L13, 
L14, L15, L16, L17, M10, 
M11, M12, M13, M14, 
M15, M16, M17, N10, 
N11, N12, N13, N14, 
N15, N16, N17, P10, P11, 
P12, P13, P14, P15, P16, 
P17, R10 to R17, T10, 
T11, T12, T23, T14, T15, 
T16, T17, U10, U11, U12, 
U13, U14, U15, U16, U17

GND

—

Ground for power supplies.

Analog power-supply ball assignment
AE11

VDDVDACRGB

—

3.3 V power supply for RGB video DAC

AE9

VDDVDACYCC

—

3.3 V power supply for YCC video DAC

AD11

GNDVDACRGB

—

Ground for RGB video DAC

AD9

GNDVDACYCC

—

Ground for YCC video DAC

AD8

SHIELDVDAC

—

Shield ground for 2 x video DACs

AE10

IREFDACRGB

—

RGB video DAC current reference

AE8

IREFDACYCC

—

YCC video DAC current reference

AC9

VREFDACRGB

—

RGB video DAC voltage reference

AC8

VREFDACYCC

—

YCC video DAC voltage reference

A10

VDDVPLL

—

Supply 3.3 V power for video PLL

C13

VDDAUDIOFSYN

—

Supply 1.8 V dedicated power for low jitter audio clock frequency synthe-
sizer

B12

GNDAUDIOFSYN

—

Dedicated ground for low jitter audio clock frequency synthesizer

C12

VDDGENFSYN

—

1.8 V dedicated power for non audio clock frequency synthesizer

B11

GNDGENFSYN

—

Dedicated ground for non audio clock frequency synthesizer

AA4

VDDAADAC

—

3.3 V power for audio DAC

AA2

VSSAADAC

—

Ground for audio DAC command switches

Y4

VDDASADAC

—

3.3 V power for audio DAC substrate

AB2

VCCAADAC

—

3.3 V power for audio DAC command switches

AB3

GNDAADAC

—

Ground for audio DAC

AC2

VCCASADAC

—

3.3 V power for audio DAC command switches substrate

AD2

IREF

—

Audio DAC output reference current

AE2

VBGFIL

—

Audio DAC filtered output reference voltage

RTC ball assignment
AF4

LPCLKIN

I

Low power clock input (1.8V tolerant).

AF5

LPCLKOSC

O

Low power clock oscillator (1.8V tolerant).

A16

NO32XTAL

I

Select for 32kHz clock source. 0:XTAL 1:Internel divider

System ball assignment
A13

CLK27MA

I

Selectable input clock to PLL or for x1 mode (5 V tolerant)

A11

CLKSPEEDSEL

I

PLL speed select (5 V tolerant)

A12

AUXCLKOUT

O

Auxiliary clock for general use (5 V tolerant)

AF6

not RESET

I

System reset (1.8 V tolerant)

AD14

not WDOGRSTOUT

O

Internal watchdog timer reset (5 V tolerant)