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LC-32RD2E/RU, LC-37RD2E/RU

6 – 25

JTAG ball assignment
AE14

TDI

I

Boundary scan test data input (5 V tolerant)

AC14

TMS

I

Boundary scan test mode select (5 V tolerant)

AF16

TCK

I

Boundary scan test clock (5 V tolerant)

AF14

not TRST

I

Boundary scan test logic reset (5 V tolerant)

AE13

TDO

O

Boundary scan test data output (5 V tolerant)

DCU ball assignment
P1

DCUTRIGGERIN

I

External trigger input to DCU (5 V tolerant)

P3

DCUTRIGGEROUT

O

Signal to trigger external debug circuitry (5 V tolerant)

Transport stream 2 ball assignment
C23

TSIN2LBYTECLK

I/O

Transport stream bit clock (5 V tolerant)

C22

TSIN2LBYTECLKVALID

I/O

Transport stream bit clock valid edge (5 V tolerant)

B23

TSIN2LERROR

I/O

Transport stream packet error (5 V tolerant)

D19

TSIN2LPACKETCLK

I/O

Transport stream packet strobe (5 V tolerant)

B18, C18, D18, C19, 
C20, D20, C21, D21

TSIN2LDATA[7:0]

I/O

Transport stream data (5 V tolerant)
(TSIN2LDATA7 is used for data input in serial mode)

Transport stream 1 ball assignment
P23

TSIN1BYTECLK

I

Transport stream bit/byte clock (5 V tolerant)

M24

TSIN1BYTECLKVALID

I

Transport stream bit/byte clock valid edge (5 V tolerant)

M26

TSIN1ERROR

I

Transport stream packet error (5 V tolerant)

N26

TSIN1PACKETCLK

I

Transport stream packet strobe (5 V tolerant)

K26, J25, H24, J24, L26, 
L25, L24, M23.

TSIN1DATA[7:0]

I

Transport stream data in (5 V tolerant)
(TSIN1DATA7 is used for data input in serial mode)

EMI ball assignment
L3

not EMIRAS or not CI_IORD

O

Row address strobe for SDRAM

K1

not_EMICAS or not_CI_IOW

O

Column address strobe for SDRAM

J1

not EMICSA 

O

Peripheral chip select A

K3

not EMICSB

O

Peripheral chip select B

K2

not EMICSC

O

Peripheral chip select C

N4

not EMICSD

O

Peripheral chip select D

J2

not EMICSE

O

Peripheral chip select E

L2

not EMICSF

O

Peripheral chip select F

L1, N3

not EMIBE[1:0]

O

External device data bus byte enable. 1 bit per byte of the data bus.

N1

notEMIOE or not_CI_OE

O

External device output enable.

N2

not EMILBA or not CI_Wea

O

Flash device load burst address.

P4

EMIWAIT not TREADY

I

External memory device target ready indicator (5 V tolerant)

P2

EMIRD not WR

O

External read/write access indicator. Common to all devices.

H3, H2, G2, H4, G4, E2, 
E1, E3, H1, D1, D2, C2, 
G3, C1, B1, A1.

EMIDATA[15:0]

I/O 

External common data bus.

D5, C5, D6, B3, A2, B2, 
A3, B4, A4, C6, B5, A5, 
D7, C7, B6, A6, B7, A7, 
D9, C9, B9, A9, B10, C11

EMIADDR[25:2]

O

External common address bus

J3

not EMIREQGNT

O

Bus request/grant indicator

K4

not EMIACKREQ

I

Bus grant/request indicator (5 V tolerant)

L4

EMIBOOTMODE0

I

External power-up port size indicator (5 V tolerant)

G1

EMISDRAMCLK

O

SDRAM clock

J4

EMIFLASHCLK

O

Peripheral clock

Programmable I/O ball assignment
W1, U4, U2, U1, R2, R1, 
T2, T1

PIO0[7:0]

I/O

Parallel input/output pin or alternative function (5 V tolerant)

AB4, Y2, AA1, Y1, W3, 
U3, W2, W4

PIO1[7:0]

I/O

AF3, AD5, AE3, AE5, 
AF2, Y3, AA3, AF1

PIO2[7:0]

I/O

AE18, AE4, AC16, AC12, 
AE6, AC11, AC5, AE12

PIO3[7:0]

I/O

AE20, AD20, AF20, 
AE19, AC17, AD18, 
AD17, AF19

PIO4[7:0]

I/O

AC22, AF22, AD21, 
AC21, AE21, AC18, 
AC20, AF21

PIO5[7:0]

I/O

LC-32RD2E/RU, LC-37RD2E/RU

6 – 26

Digital audio ball assignment
AF17

SCLK

O

Serial clock (5 V tolerant)

AE17

PCMDATA1

O

PCM data out (5 V tolerant)

AE16

PCMCLK

I/O

External PCM clock input or internal PCM clock output (5 V tolerant)

AF18

LRCLK

O

Left/right clock (5 V tolerant)

AD16

SPDIF

O

Digital audio output (5 V tolerant)

Audio/video core SDRAM ball assignment (SMI)
AD26, AB25, AB24, 
AC25, AE26, AB23, 
AE25, AF26, AD25, 
AF25, AE24, AF24, 
AF23, AE23.

SMIADDR[13:0]

O

SDRAM address bus.

U26, U25, R23, V26, 
V25, T23, V24, V23, 
W26, W25, Y25, Y26, 
Y23, AB26, Y24, AC26.

SMIDATA[15:0]

I/O

SDRAM data bus.

T24

not SMICS0

O

SDRAM chip select for 1st SDRAM.

T25

not SMICS1

O

SDRAM chip select for 2nd 16 Mbit SDRAM.

T26

not SMICAS

O

SDRAM column address strobe.

R24

not SMIRAS

O

SDRAM row address strobe.

R25

not SMIWE

O

SDRAM write enable.

P26

SMIMEMCLKIN

I

SDRAM memory clock input.

R26

SMIMEMCLKOUT

O

SDRAM memory clock output.

P24

SMIDATAML

O

SDRAM data bus lower byte enable

P25

SMIDATAMU

O

SDRAM data bus upper byte enable

IEEE 1284 ball assignment
B15, A15, D16, C16, B16, 
B17, C17, D17

P1284DATA[7:0]

I/O

1284 AV data (5V tolerant).

C15

notP1284SELECTIN

I/O

1284 AV control signals (5V tolerant).

D15

notP1284INIT

I/O

A14

notP1284FAULT

I/O

B14

notP1284AUTOFD

I/O

C14

P1284SELECT

I/O

D14

P1284PERROR

I/O

D13

P1284BUSY

I/O

D12

notP1284ACK

I/O

D11

notP1284STROBE

I/O

Interrupt ball assignment
T4, R4, T3, R3

INTERRUPT[3:0]

I/O

External interrupts (5 V tolerant)

Analog audio DAC (digital-to-analog converter) ball assignment
AE1

OUTPLEFT

O

Left channel, differential positive current output

AC1

OUTMLEFT

O

Left channel, differential negative current output

AD1

OUTPRIGHT

O

Right channel, differential positive current output.

AB1

OUTMRIGHT

O

Right channel, differential negative current output.

Analog video DAC ball assignment
AF12

ROUT

O

Red output.

AF11

GOUT

O

Green output.

AF13

BOUT

O

Blue output.

AF8

COUT

O

Chroma output.

AF9

CVOUT

O

Composite video output.

AF10

YOUT

O

Luma output.

Digital video ball assignment
AD22

not HSYNC

I/O

Horizontal sync (5V tolerant).

AE22

EVEN not ODD

I/O

Vertical sync (5V tolerant).

LC-32RD2E/RU, LC-37RD2E/RU

6 – 27

38

CLK

I

Active on the positive going edge to sample all inputs.

19

CS

I

Disables or enables device operation by masking or enabling all inputs except CLK, CKE and 
DQM.

37

CKE

I

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.

23

A0

I

Row/column addresses are multiplexed on the same pins.
Row address: RA0-RA11,
Column address: CA0-CA7

24

A1

I

25

A2

I

26

A3

I

29

A4

I

30

A5

I

31

A6

I

32

A7

I

33

A8

I

34

A9

I

22

A10

I

35

A11

I

20, 21

BA0, BA1

I

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

18

RAS

I

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

LC-32RD2E/RU, LC-37RD2E/RU

6 – 28

17

CAS

I

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

16

WE

I

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

15

LDQM

I

Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.

39

UDQM

I

2

DQ0

I/O

Data inputs/outputs are multiplexed on the same pins.

4

DQ1

I/O

5

DQ2

I/O

7

DQ3

I/O

8

DQ4

I/O

10

DQ5

I/O

11

DQ6

I/O

13

DQ7

I/O

42

DQ8

I/O

44

DQ9

I/O

45

DQ10

I/O

47

DQ11

I/O

48

DQ12

I/O

50

DQ13

I/O

51

DQ14

I/O

53

DQ15

I/O

1, 14, 27

VDD

—

Power for the input buffers and the core logic.

28, 41, 54

VSS

—

Ground for the input buffers and the core logic.

3, 9, 43, 49

VDDQ

—

Isolated power supply for the output buffers to provide improved noise immunity.

6, 12, 46, 52

VSSQ

—

Isolated ground for the output buffers to provide improved noise immunity.

40

N.C/RFU

—

This pin is recommended to be left No Connection on the device.

36

N.C

—