DOWNLOAD Sharp LC-37RD2E (serv.man6) Service Manual ↓ Size: 1.52 MB | Pages: 30 in PDF or view online for FREE

Model
LC-37RD2E (serv.man6)
Pages
30
Size
1.52 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Major IC Informations
File
lc-37rd2e-sm6.pdf
Date

Sharp LC-37RD2E (serv.man6) Service Manual ▷ View online

LC-32RD2E/RU, LC-37RD2E/RU
6 – 9
28
CSCL
I
Configuration I2C Clock. 5 V Tolerant
27
CSDA
I/O
Configuration I2C Data. 5 V Tolerant
103
SCDT
O
Indicates active video at HDMI input port
107
CLK48B
I/O
Data Bus Latch Enable
34
R0PWR5V
I
Port 0 Transmitter Detect. 5V Tolerant
33
R1PWR5V
I
Port 1 Transmitter Detect. 5V Tolerant
101
RSVDL
I
Reserved, must be tied LOW
56
RSVD_A
Reserved Pin, leave unconnected
6, 7, 8, 10, 11, 12, 13, 14, 17, 18, 
19, 20, 81, 82, 83, 87, 93, 100
NC
No internal connection
9
EVNODD
O
Indicates. Even or Odd field for interlaced formats. Polarity programmable in register
Differential Signal Data Pins
40
R0XC+
I
HDMI Port 0. TMDS input clock pair
39
R0XC-
I
44
R0X0+
I
HDMI Port 0. TMDS input data pair
43
R0X0-
I
48
R0X1+
I
HDMI Port 0. TMDS input data pair
47
R0X1-
I
52
R0X2+
I
HDMI Port 0. TMDS input data pair
51
R0X2-
I
59
R1XC+
I
HDMI Port 1. TMDS input clock pair
58
R1XC-
I
63
R1X0+
I
HDMI Port 1. TMDS input data pair
62
R1X0-
I
67
R1X1+
I
HDMI Port 1. TMDS input data pair
66
R1X1-
I
71
R1X2+
I
HDMI Port 1. TMDS input data pair
70
R1X2-
I
Power and Ground Pins
22, 23, 35, 74, 79, 92, 105, 114, 
128, 139
CVCC18
Digital Logic VCC
21, 24, 36, 73, 80, 91, 106, 115, 
127, 138
CGND
Digital Logic GND
5, 16, 26, 76, 89, 109, 122, 134
IOVCC
Input/Output Pin Supply (3.3V)
4, 15, 25, 75, 90, 108, 120, 135
IOGND
Input/Output Pin Ground
38, 42, 46, 50, 57, 61, 65, 69
AVCC
TMDS Analog VCC
41, 45, 49, 53, 60, 64, 68, 72
AGND
TMDS Analog GND
37
PVCC0
TMDS Port 0 PLL VCC
55
PVCC1
TMDS Port 1 PLL VCC
54
TMDSPGND
TMDS PLL GND
94
AUDPVCC18
ACR PLL VCC
95
AUDPGND
ACR PLL GND
98
XTALVCC
ACR PLL Crystal Input VCC
99
REGVCC
ACR PLL Regulator VCC
Pin No.
Pin Name
I/O
Pin Function
LC-32RD2E/RU, LC-37RD2E/RU
6 – 10
2.6. IC2301 (RH-iXC009WJZZQ)
2.6.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1
GND
Ground
2
8MHz_IN
I
Crystal oscillator input
3
8MHz_OUT
O
Crystal oscillator output
4
TEST
I
Terminal for shipping test. Fixed to “L” level
5
3.3V
Power supply (+3.3 V)
6
FRC_BUS_SW
O
FRC_BUS_SW
7
32kHz_OUT
O
N.C
8
RESET
I
RESET input terminal
9
P20
N.C
10
P00
N.C
11
UART-RXD1
I
For flash write
12
UART-TXD1
O
For flash write
13
CEC-IN
I
CEC
14
P04
I
N.C
15
P05
O
N.C
16
CEC-OUT
O
CEC
17
CEC-IN2
I
CEC
18
VAREF
Analog reference voltage input terminal for AD conversion
19
AVDD
Analog power supply (+3.3 V)
20
AIN0
I
Temperature sensor
21
AIN1
I
N.C
22
AIN2
I
OPC input
23
AIN3
I
N.C
24
POW_ERR
I
Power supply detection
25
FAN_ERR
I
FAN detection
26
BL_ERR
I
Backlight detection
27
SV1JSW
I
S end detection
28
QS_EN
O
Panel controller QS
29
FRAME
O
50/60Hz switching
30
T1
I
Panel controller TEMP
31
T2
I
Panel controller TEMP
32
T3
I
Panel controller TEMP
33
BANKSEL
O
Panel controller
34
R/L
O
Panel controller. Flip horizontal.
35
U/D
O
Panel controller. Flip vertical.
36
DTVHDMI
O
DTV-HDMI switching (H, V, Audio)
37
DTVPC
O
DTV-PC switching (H, V, Audio)
38
SCART12
O
SCART switching
39
IN3/EX
O
IN3 switching
40
DTU_IN3Y
O
N.C
41
ANT+5V_SW
O
ANT+5V control
42
DTN_BUS_SEL
O
D-TUNER I2C select
43
DTM_RST
O
DTV PWB reset
44
TCON_WP
O
Counter adjustment write-protect
45
LVDS_PWDN
O
LVDS_MUTE
46
E2
N.C
47
PFC_ON
O
PFC_SW
48
PCON1
O
Power SW1 MAIN
49
PCON2
O
Power SW2 INVERTER
50
PCON3
O
Power SW3 LCD+12 V
51
BL_ON
O
N.C
52
SCL
I
I2C Slave clock
53
SDA
I/O
I2C Slave data
54
I-REQ
O
Sub-microprocessor interrupt
55
SCL_F
I
I2C clock
56
SDA_F
I/O
I2C data
57
LEDPOW_R
O
Power R_LED ON (SVMOUT)
58
LEDPOW_G
O
Power G_LED ON (BOUT)
59
LEDSLP
O
Sleep_LED ON
60
LEDOPC
O
OPC_LED ON
61
MUTE_SP
O
Mute
LC-32RD2E/RU, LC-37RD2E/RU
6 – 11
62
S_MUTE
O
Mute
63
S2_MUTE
O
Mute SCART2
64
IREM_SW
O
Magerinc (IR-PATH)
Pin No.
Pin Name
I/O
Pin Function
LC-32RD2E/RU, LC-37RD2E/RU
6 – 12
2.7. IC2361 (VHiTLVD823+-1Q)
2.7.1 Block Diagram
2.7.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
48, 49
TA1+, TA1-
O
The 1st Link. The 1st pixel output data when Dual Link.
46, 47
TB1+, TB1-
O
43, 44
TC1+, TC1-
O
39, 40
TD1+, TD1-
O
41, 42
TCLK1+, TCLK1-
O
LVDS Clock Out for 1st Link.
36, 37
TA2+, TA2-
O
The 2nd Link. These pins are disabled when Single Link.
34, 35
TB2+, TB2-
O
31, 32
TC2+, TC2-
O
27, 28
TD2+, TD2-
O
29, 30
TCLK2+, TCLK2-
O
LVDS Clock Out for 2st Link.
60, 59, 58, 57, 54, 53, 52, 51
R[17:10]
I
The 1st Pixel Data Inputs.
68, 67, 66, 65, 64, 63, 62, 61
G[17:10]
I
78, 77, 76, 75, 74, 73, 70, 69
B[17:10]
I
86, 85, 84, 83, 82, 81, 80, 79
R[27:20]
I
The 2st Pixel Data Inputs.
96, 95, 94, 93, 92, 91, 90, 89
G[27:20]
I
6, 5, 2, 1, 100, 99, 98, 97
B[27:20]
I
9
DE
I
Data Enable Input.
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