Sharp LC-37RD2E (serv.man6) Service Manual ▷ View online
LC-32RD2E/RU, LC-37RD2E/RU
6 – 2
1.7. IC1951 (VHiSii9025+-1Q)
The Sii9025 is a compliant with the latest HDMI 1.2 (High Definition Multimedia Interface) specification.
Backward compatibility with DVI 1.0 allows HDMI systems to connect to existing DVI 1.0 hosts.
The SiI9025 is capable of receiving and outputting two channel digital audio at up to 192 kHz- an excellent solution for Digital TVs.
An S/PDIF port supports up to 192 kHz audio.
The SiI9025 also comes pre-programmed with HDCP keys, greatly simplifying the manufacturing process, while providing the highest level of HDCP
key security.
key security.
1) Dual-Input HDMI 1.2, HDCP 1.1 and DVI 1.0 compliant receiver.
2) Integrated TMDSR core.
3) Digital video interface supports video processors:
• 24-bit RGB/YCbCr 4:4:4
• 16/20/24-bit YCbCr 4:2:2
• 8/10/12-bit YCbCr 4:2:2 (ITU BT.656)
• 12-bit DMO (Digital Multimedia Output) RGB/YCbCr 4:4:4 (clocked with rising & falling edges)
• Color Space Conversion for both RGB-to-YCbCr and YCbCr-to-RGB (both 601 and 709)
• Auto video mode configuration simplifies system firmware design.
4) Digital audio interface supports high-end audio systems:
• One programmable I2S output for connection to low-cost DACs at 32-192kHz.
• S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission (32-192 kHz Fs) using IEC60958 and IEC61937.
• Auto audio error detection with programmable soft mute.
5) Integrated HDCP decryption engine for receiving protected audio and video content.
6) HDCP Built in Self Test (BIST) lowers cost to test HDCP operation.
7) Pre-programmed HDCP keys provide highest level of key security, simplifies manufacturing.
1.8. IC2361 (VHiTLVD823+-1Q)
The TLVD823 is a 170MHz LVDS (Low Voltage Differential Signaling) 48-bit interface chip set for transmission. It is an LSI for serializing and transmit-
ting RGB signal, HD, VD, blanking signal and pixel clock.
ting RGB signal, HD, VD, blanking signal and pixel clock.
LVDS is a method for transmitting high-speed digital signal via cable driven by low-amplitude differential signal. 1 LINK consists of five pairs of differ-
ential signals.
ential signals.
The TA, TB, TC, and TD pairs are used for data transmission, and the TCLK pair is used for pixel clock transmission. Seven data bits of TA, TB, TC
and TD each (28 in total) are transmitted per pixel clock.
and TD each (28 in total) are transmitted per pixel clock.
The input RGB (48 bit) signal and sync signal (HD, VD and DE) are allocated to the 56 data which are equal to 2 LINK. The output digital video signal
is sent to the LCD controller circuit.
is sent to the LCD controller circuit.
1.9. IC301/302 (VHiTDA8931T-1Y)
The TDA8931 is a switching power stage for high efficiency class-D audio power amplifier systems.
With this amplifier a compact 1x 20 W closed loop self-oscillating digital amplifier system can be built.
The audio output of LC-32/37RD2E are set to 10W, respectively.
1.10. IC4203 (RH-iXB681WJZZQ)
This IC is a high performance CMOS super technology 16Mbit Flash Memory.
Start software (loader) for the CPU with a built-in digital processor and application software have been written on this Flash Memory.
The digital processor reads these soft wares on start-up and implements them.
1.11. IC4201/4702 (RH-iXB742WJZZQ)
This IC is 64Mb SDRAM (static dynamic random-access memory) IC.
In this equipment, it is used for SMI memory (for image processing), and data is used for operation of the digital processor.
1.12. IC4001 (RH-IXB680WJZZQ)
This is a video/ audio signal processing IC (Digital Processor) (STi5516) for digital tuner, which has been manufactured by ST Microelectronics, and
incorporates a CPU.
incorporates a CPU.
In this equipment, it implements GUI processing and video/audio processing for digital tuner, negotiation processing with CI-CARD, etc.
1.13. IC1702/1741/1758 (VHIMP1415C+-1Y)
The MP1415C is a monolithic step-down switch mode Converter with a built-in internal power MOSFET. It actives 2A continuous output current over
a wide input supply range with excellent load and line regulation.
a wide input supply range with excellent load and line regulation.
Current mode operation provides fast transient response and eases loop stabilization.
Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown.
LC-32RD2E/RU, LC-37RD2E/RU
6 – 3
2. Detailed ICs Information
2.1. IC201 (VHiTDA9886+-1Y)
2.1.1 Block Diagram
2.1.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1
VIF1
I
VIF differential input1
2
VIF2
I
VIF differential input2
3
OP1
O
Output1 (open-collector)
4
FMPLL
—
FM-PLL for loop filter
5
DEEM
O
De-emphasis output for capacitor
6
AFD
I
AF decoupling input for capacitor
7
DGND
—
Digital ground
8
AUD
O
Audio output
9
TOP
—
Tuner AGC TakeOver Point (TOP)
10
SDA
I/O
I2C-bus data input/output
11
SCL
I
I2C-bus clock input
12
SIOMAD
O
Sound intercarrier output and MAD select
13
N.C
—
Not connected
14
TAGC
O
TAGC14tuner AGC output
15
REF
I
4MHz crystal or reference input
16
VAGC
—
VIF-AGC for capacitor
17
CVBS
O
Video output
18
AGND
—
Analog ground
19
VPLL
—
VIF-PLL for loop filter
20
VP
—
Supply voltage (+5 V)
21
AFC
O
AFC output
22
OP2
O
Output2 (open-collector)
23
SIF1
I
SIF differential input1
24
SIF2
I
SIF differential input2
LC-32RD2E/RU, LC-37RD2E/RU
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2.2. IC202 (RH-iXB964WJZZQ)
2.2.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
Clock and resets
32
32
NOT_RESET
I
Hardware reset, active low
15
XTAL_I
I
Analog Crystal oscillator input/external clock (2.5 V)
14
XTAL_O
O
Analog Crystal oscillator output
13
VDDA_2V5
—
Supply Analog oscillator supply (2.5 V)
16
VDDA_2V5
—
Supply Analog PLL supply (2.5 V)
Analog interface
1
1
RF_LEVEL
—
ADC 8 input for RF level monitoring
2
VDDA_2V5
—
Analog ADC 8 supply (2.5 V)
3
QP
—
Positive Q analog input for baseband configuration
4
QM
—
Negative Q analog input for baseband configuration
5
VDDA_ISO
—
Analog ISO nwell polarization (2.5 V)
6
VDDA_2V5
—
Analog ADC 12 supply (2.5 V)
7
REFP
—
Internal positive reference
8
REFM
—
Internal negative reference
9
INCM
—
Internal common mode
10
IM
—
Negative I analog input for IF and baseband configuration
11
IP
—
Positive I analog input for IF and baseband configuration
12
VDDA_1.0
—
Analog supply (1.0 V)
I2C interface
29
29
SDA
I/O
Serial data (open drain)
30
SCL
I
Serial clock (open drain)
21
SDAT
I/O
SDA tuner (open drain)
20
SCLT
I
SCL tuner
MPEG interface
43
43
D7
O
Serial MPEG data or parallel MPEG data (bit 7)
42
D6
O
Parallel MPEG data (bit 6)
40
D5
O
Parallel MPEG data (bit 5)
39
D4
O
Parallel MPEG data (bit 4)
37
D3
O
Parallel MPEG data (bit 3)
36
D2
O
Parallel MPEG data (bit 2)
35
D1
O
Parallel MPEG data (bit 1)
33
D0
O
Parallel MPEG data (bit 0)
44
CLK_OUT
O
MPEG byte or bit clock
46
STR_OUT
O
MPEG first byte sync
47
D/NOT_P
O
MPEG data valid/parity
48
ERROR
O
MPEG packet error
Front end controls
18
18
AGC_RF
I/O
RF AGC control
(5 V tolerant)
17
AGC_IF
I/O
IF AGC control
(5 V tolerant)
64
TEST
I/O
Reserved test mode, must be grounded.
27
GPIO0
I/O
General-purpose input/output port 0. Reserved test mode, must be grounded.
49
GPIO1
I/O
General-purpose input/output port 1
60
GPIO2
I/O
General-purpose input/output port 2 or lock indicator
59
GPIO3
I/O
General-purpose input/output port 3 or lock indicator
58
GPIO4
I/O
General-purpose input/output port 4
57
GPIO5
I/O
General-purpose input/output port 5
54
GPIO6
I/O
General-purpose input/output port 6
53
GPIO7
I/O
General-purpose input/output port 7
52
GPIO8
I/O
General-purpose input/output port 8. Reserved test mode, must be grounded.
61
GPIO9
I/O
General-purpose input/output port 9
23
AUX_CLK
I/O
Auxiliary clock
25
CS0
I
Chip select LSB
26
CS1
I
Chip select MSB
Power supply
19, 24, 31, 38,
45, 51, 55, 62
19, 24, 31, 38,
45, 51, 55, 62
VDD_1V0
—
Digital core supply (1.0 V)
22, 28, 34, 41,
50, 56, 63
50, 56, 63
VDD_3V3
—
Digital I/O supply (3.3 V)
LC-32RD2E/RU, LC-37RD2E/RU
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2.3. IC301/IC302 (VHiTDA8931T-1Y)
2.3.1 Block Diagram