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CLK27MA

A

A18

I

Selectable input clock to PLL or for x1 mode

C4

CLKSPEEDSEL

a

C16

I

PLL speed select

C4

AUXCLKOUT

a

D17

O

Auxiliary clock for general use

C4

NOT_RESET

B

AE7

I

System reset

-

NOT_WDOGRSTOUT

a

AF8

O

Internal watchdog timer reset.

C4

a. 5 V tolerant
b. 1.8 V tolerant

TDI

A

AC7

I

Boundary scan test data input

C4

TMS

a

AD7

I

Boundary scan test mode select

C4

TCK

a

AF7

I

Boundary scan test clock

-

NOT_TRST

a

AE6

I

Boundary scan test logic reset

C4

TDO

a

AF6

O

Boundary scan test data output

C4

a. 5 V tolerant

DCUTRIGGERIN

a

P1

I

External trigger input to DCU

C4

DCUTRIGGEROUT

A

R3

O

Signal to trigger external debug circuitry

C4

a. 5 V tolerant

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NOT_EMIRAS or
NOT_CI_IORD

a

J2

O

Row address strobe for SDRAM

C4

NOT_EMICAS or
NOT_CI_IOW

a

J1

O

Column address strobe for SDRAM

E8

NOT_EMICSA

K4

O

Peripheral chip select A

E8

NOT_EMICSB

K3

O

Peripheral chip select B

E8

NOT_EMICSC

K2

O

Peripheral chip select C

E8

NOT_EMICSD

K1

O

Peripheral chip select D

E8

NOT_EMICSE

L4

O

Peripheral chip select E

E8

NOT_EMICSF

L3

O

Peripheral chip select F

E8

NOT_EMIBE[1:0]

L1, L2

O

External device data bus byte enable. 1 bit per
byte of the data bus.

E8

NOT_EMIOE or
NOT_CI_OE

M1

O

External device output enable.

E8

NOT_EMILBA or
NOT_CI_WEA

N3

O

Flash device load burst address.

E8

EMIWAITNOTTREADY

b

N4

I

External memory device target ready indicator

C4

EMIRDNOTWR

N2

O

External read/write access indicator. Common to
all devices.

E8

EMIDATA[15:0]

c

I/O

External common data bus.

E8

EMIADDR[25:2]

d

e

O

External common address bus

E8

NOT_EMIREQGNT

J3

O

Bus request/grant indicator

E8

NOT_EMIACKREQ

b

H1

I

Bus grant/request indicator

C4

EMIBOOTMODE0

b

H3

I

External power-up port size indicator

C4

EMISDRAMCLK

A1

O

SDRAM clock

E8

EMIFLASHCLK

A2

O

Peripheral clock

E8

a. Or equivalent ATA HDD interface signal.
b. 5 V tolerant
c. B3, A3, A4, B4, C4, A5, B5, C5, A6, B6, C6, D6, A7, B7, C7 and A8.
d. EMIADDR[19:20] are used as ATA HDD interface function: ATA CS0 and CS1. There is no

interconnect configuration control register bit to select this function. The addresses are just
reused as chip selects.

e. B8, C8, A9, B9, C9, D9, A10, B10, C10, A11, B11, C11, A12, B12, C12, D12, A13, B13, C13,

D13, A14, B14, C14 and D14.

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TSIN2LBYTECLK

a

L24

I/O

Transport stream bit clock

C4

TSIN2LBYTECLKVALID

a

L26

I/O

Transport stream bit clock valid edge

C4

TSIN2LERROR

a

L25

I/O

Transport stream packet error

C4

TSIN2LPACKETCLK

a

J25

I/O

Transport stream packet strobe

C4

TSIN2LDATA[7:0]

a

b c

I/O

Transport stream data

C4

a. 5 V tolerant
b. H25, H24, H23, J26, J24, K26, K25 and K24
c. TSIN2LDATA7 is used for data input in serial mode.

TSIN1BYTECLK

a

P23

I

Transport stream bit/byte clock

C4

TSIN1BYTECLKVALID

a

P26

I

Transport stream bit/byte clock valid edge

C4

TSIN1ERROR

a

P25

I

Transport stream packet error

C4

TSIN1PACKETCLK

a

P24

I

Transport stream packet strobe

C4

TSIN1DATA[7:0]

a

b

,

c

I

Transport stream data in

C4

a. 5 V tolerant
b. M26, M25, M24, M23, N26, N25, N24 and N23.
c. TSIN1DATA7 is used for data input in serial mode.

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PIO0[0:7]

A

b

I/O

Parallel input/output pin or alternative function

P4

PIO1[0:7]

a

c

I/O

P4

PIO2[0:7]

a

d

I/O

P4

PIO3[0:7]

a

e

I/O

P4

PIO4[0:7]

a

f

I/O

P4

PIO5[0:7]

a

g

I/O

P4

a. 5 V tolerant
b. U2, U1, U3, V4, V3, V2, V1 and W4
c. W3, W2, W1, Y3, Y2, Y1, AA4 and AE1
d. AF1, AD2, AE2, AF2, AF3, AD3, AE3 and AD4
e. AE5, AE4, AF5, AF4, AD6, AD15, AD5 and AE15
f. AF15, AD16, AE16, AF16, AC17, AD17, AF18 and AE17
g. AF17, AD18, AE18, AC19, AD19, AE19, AF19 and AD20

SCLK

B

AD13

O

Serial clock

C4

PCMDATA[1]

b

AE14

O

PCM data out

C4

PCMCLK

b

AE13

I/O

External PCM clock input or internal PCM clock
output

C4

LRCLK

b

AF13

O

Left/right clock

C4

SPDIF

b

AC15

O

Digital audio output

C4

a. Note: Digital audio input pins PCMI_SCLK, PCMI_DATA and PCMI_LRCLK are alternate

functions for NOT_CD_REQ[1], I1284HOSTLOGICHIGH, and NOT_CD_REQ[0], on PIO port
3 bits [6:4]

b. 5 V tolerant