Sharp LC-32P70E (serv.man10) Service Manual ▷ View online
78
LC-26GA5E
LC-32GA5E
LC-26P70E
LC-32P70E
LC-37P70E
2003 Oct 02
8
Philips Semiconductors
Product specification
I
2
C-bus controlled single and multistandard
alignment-free IF-PLL demodulators
TDA9885; TDA9886
7
PINNING
SYMBOL
PIN
DESCRIPTION
TDA9885T
TDA9885TS
TDA9886T
TDA9886TS
TDA9885HN TDA9886HN
VIF1
1
1
30
30
VIF differential input 1
VIF2
2
2
31
31
VIF differential input 2
n.c.
−
−
32
32
not connected
OP1
3
3
1
1
output port 1; open-collector
FMPLL
4
4
2
2
FM-PLL for loop filter
DEEM
5
5
3
3
de-emphasis output for capacitor
AFD
6
6
4
4
AF decoupling input for capacitor
DGND
7
7
5
5
digital ground
n.c.
−
−
6
6
not connected
AUD
8
8
7
7
audio output
TOP
9
9
8
8
tuner AGC TakeOver Point (TOP) for resistor
adjustment
adjustment
SDA
10
10
9
9
I
2
C-bus data input and output
SCL
11
11
10
10
I
2
C-bus clock input
SIOMAD
12
12
11
11
sound intercarrier output and MAD select with
resistor
resistor
n.c.
−
−
12
12
not connected
n.c.
13
13
13
13
not connected
n.c.
−
−
14
14
not connected
TAGC
14
14
15
15
tuner AGC output
REF
15
15
16
16
4 MHz crystal or reference signal input
VAGC
−
16
−
17
VIF-AGC for capacitor
n.c.
16
−
17
−
not connected
CVBS
17
17
18
18
composite video output
n.c.
−
−
19
19
not connected
AGND
18
18
20
20
analog ground
VPLL
19
19
21
21
VIF-PLL for loop filter
V
P
20
20
22
22
supply voltage
AFC
21
21
23
23
AFC output
OP2
22
22
24
24
output port 2; open-collector
n.c.
−
−
25
25
not connected
SIF1
23
23
26
26
SIF differential input 1 and MAD select with
resistor
resistor
SIF2
24
24
27
27
SIF differential input 2 and MAD select with
resistor
resistor
n.c.
−
−
28
28
not connected
n.c.
−
−
29
29
not connected
2.4.2. Pinning
79
LC-26GA5E
LC-32GA5E
LC-26P70E
LC-32P70E
LC-37P70E
2.4.2. Pinning (Continued)
2003 Oct 02
9
Philips Semiconductors
Product specification
I
2
C-bus controlled single and multistandard
alignment-free IF-PLL demodulators
TDA9885; TDA9886
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TDA9885T
TDA9886T
TDA9886T
MHC109
VIF1
VIF2
OP1
FMPLL
DEEM
AFD
DGND
AUD
TOP
SDA
SCL
SIOMAD
SIF2
SIF1
OP2
AFC
VP
VPLL
AGND
CVBS
VAGC
(1)
REF
TAGC
n.c.
Fig.2 Pin configuration for SO24.
(1) Not connected for TDA9885T.
handbook, halfpage
TDA9885TS
TDA9886TS
TDA9886TS
MHC110
VIF1
VIF2
OP1
FMPLL
DEEM
AFD
DGND
AUD
TOP
SDA
SCL
SIOMAD
SIF2
SIF1
OP2
AFC
VP
VPLL
AGND
CVBS
VAGC
(1)
REF
TAGC
n.c.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Fig.3 Pin configuration for SSOP24.
(1) Not connected for TDA9885TS.
handbook, halfpage
MHC111
TDA9885HN
TDA9886HN
TDA9886HN
OP2
FMPLL
OP1
AFC
DEEM
VP
AFD
VPLL
DGND
AGND
n.c.
n.c.
AUD
CVBS
TOP
VAGC
(1)
n.c.
VIF2
VIF1
n.c.
n.c.
SIF2
SIF1
n.c.
SDA
SCL
SIOMAD
n.c.
n.c.
n.c.
TAGC
REF
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
terminal 1
index area
Fig.4 Pin configuration for HVQFN32.
Bottom view.
(1) Not connected for TDA9885HN.
(1) Not connected for TDA9885HN.
80
LC-26GA5E
LC-32GA5E
LC-26P70E
LC-32P70E
LC-37P70E
2.5. IC202 (STV0360)
2.5.1. Pinning
Pin information
STV0360
6/66
STMicroelectronics Confidential
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3
Pin information
3.1
Pin connections (preliminary)
Figure 3: Pin out for 64-pin TQFP (10 x 10 mm)
X
TA
LO
G
N
D
X
TA
L
T
E
S
T
X
TA
LI
D
2
G
N
D
S
D
A
S
T
R
_O
U
T
G
N
D
D
7
D
6
V
D
D
D
4
S
C
LT
S
D
AT
S
C
L
T
E
S
T
AGC1
AGC2
INP
DGNDA
DVCCA1.8
GNDA
D1
LOCK/OP2
GND
AUX_CLK
GND
GND
OP0
CIQ/HFEC3
1
2
3
4
5
6
7
8
9
10
11
12
13
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
62 61 60 59 58 57 56 55
63
54 53 52 51 50 49
17
19 20 21 22 23 24 25 26
18
27 28 29 30 31 32
D
5
VCCA1.8
REFP
GNDA
RESET
VDD
VDD_3.3
LOCK/OP1
GND
ERROR
VDD
D/P
ERROR
VDD
D/P
CLK_OUT
VDD_3.3
D0
VDD_3.3
D0
D
3
V
D
D
_3
.3
V
C
C
X
TA
L1
.8
VR
VCCA3.3
REFM
INM
GND
IP
0
V
D
D
G
N
D
C
S
0
C
S
1
G
N
D
V
D
D
_3
.3
H
F
E
C
0
C
C
LK
/H
F
E
C
1
C
D
AT
A
/.H
F
E
C
2
VDD_3.3: 3.3V output buffer supply
VDD: 1.8V core and input buffer supply
VDD: 1.8V core and input buffer supply
GND: both core and buffer ground
TQFP64
STV0360
VDD
G
N
D
81
LC-26GA5E
LC-32GA5E
LC-26P70E
LC-32P70E
LC-37P70E
2.5.2. Pin Description
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STMicroelectronics Confidential
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STV0360
Pin information
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3.2
Pinout description (preliminary)
Table 1: STV0360 pin description
Pin number
Name
Type
Description
Drive (mA)
Clock and resets
12
RESET
I
1
Hardware reset, active low
-
62
XTALI
Analog
Crystal oscillator input/external clock (1.8 V)
-
63
XTALO
Analog
Crystal oscillator output
-
61
VCCXTAL1.8
Supply
Analog oscillator supply (1.8 V)
-
64
GNDXTAL
Ground
Analog oscillator ground
-
Analog interface
2
DVCCA1.8
Supply
Analog part digital supply (1.8 V)
-
5
REFM
Analog
Internal negative reference
-
6
REFP
Analog
Internal positive reference
3
VCCA1.8
Supply
Analog supply (1.8 V)
-
9
INM
Analog
Negative analog input
-
10
INP
Analog
Positive analog input
-
4, 11
GNDA
Supply
Analog ground
-
1
DGNDA
Ground
Analog ground
-
7
VR
Analog
Reference
-
8
VCCA3.3
Supply
Analog supply (3.3 V)
I
2
C interface
21
SDA
IO
2
Serial data (open drain)
8
20
SCL
I
Serial clock (open drain)
-
19
SDAT
IO
SDA tuner (open drain)
4
18
SCLT
I
SCL tuner
MPEG interface
25, 26, 27, 29,
31, 32, 33, 34
31, 32, 33, 34
D7/0
O
3
Serial D7, MPEG data
8/4
36
CLK_OUT
O
MPEG byte or bit clock
4
23
STR_OUT
O
MPEG first byte sync
2
38
D/P
O
MPEG data valid/parity
4
40
ERROR
O
MPEG packet error
2
51
HFEC0
O
Hierarchical FEC output bit 0
2
50
CCLK/HFEC1
O
Hierarchical FEC output bit 1 or clock for
constellation display
constellation display
2
49
CDATA/HFEC2
O
Hierarchical FEC output bit 2 or data for
constellation display
constellation display
2
48
CIQ/HFEC3
O
Hierarchical FEC output bit 3 or IQ validation for
constellation display
constellation display
2
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