DOWNLOAD Sharp LC-32P70E (serv.man10) Service Manual ↓ Size: 542.65 KB | Pages: 41 in PDF or view online for FREE

34/709

STMicroelectronics Confidential

  7368868E

Confidential

SMIADDR[13:0]

a

O

Audio/video core SDRAM address bus

S8

SMIDATA[15:0]

b

I/O

Audio/video core SDRAM data bus

S8

NOT_SMICS0

V25

O

Audio/video core SDRAM chip select for 1st
SDRAM

S8

NOT_SMICS1

V26

O

Audio/video core SDRAM chip select for 2nd
16 Mbit SDRAM

S8

NOT_SMICAS

U23

O

Audio/video core SDRAM column address strobe

S8

NOT_SMIRAS

U24

O

Audio/video core SDRAM row address strobe

S8

NOT_SMIWE

U25

O

Audio/video core SDRAM write enable

S8

SMIMEMCLKIN

T23

I

Audio/video core SDRAM memory clock input

S8b

SMIMEMCLKOUT

U26

O

Audio/video core SDRAM memory clock output

S8

SMIDATAML

T24

O

Audio/video core SDRAM data bus lower byte
enable

S8

SMIDATAMU

T25

O

Audio/video core SDRAM data bus upper byte
enable

S8

a. AC24, AC23, AD26, AD25, AD24, AD23, AE26, AE25, AE24, AE23, AF26, AF25, AF24 and

AF23.

b. V24, W26, W25, W24, W23, Y26, Y25, Y24, AA26, AA25, AA24, AB26, AB25, AB24, AC26

and AC25.

P1284DATA[7:0]

A

b

I/O

1284 data or 1394 AV data

I14

NOT_P1284SELECTIN

a

E24

I/O

1284 or 1394 AV control signals

I14

NOT_P1284INIT

a

E25

I/O

I14

NOT_P1284FAULT

a

E26

I/O

I14

NOT_P1284AUTOFD

a

D24

I/O

I14

P1284SELECT

a

D25

I/O

I14

P1284PERROR

a

D26

I/O

I14

P1284BUSY

a

C25

I/O

I14

NOT_P1284ACK

a

C26

I/O

I14

NOT_P1284STROBE

a

B26

I/O

I14

a. 5 V tolerant
b. F26, F25, F24, F23, G26, G25, G24 and H26.

 7368868E

STMicroelectronics Confidential

35/709

Confidential

INTERRUPT[3:0]

A

b

I/O

External interrupts

C4

a. 5 V tolerant
b. T1, T2, T3 and T4.

OUTPLEFT

AC3

O

Left channel, differential positive current output

OUTMLEFT

AB1

O

Left channel, differential negative current output

OUTPRIGHT

AC4

O

Right channel, differential positive current output

OUTMRIGHT

AB4

O

Right channel, differential negative current output

ROUT

AF11

O

Red output

GOUT

AE11

O

Green output

BOUT

AD12

O

Blue output

COUT

AF9

O

Chroma output

CVOUT

AD10

O

Composite video output

YOUT

AE10

O

Luma output

NOT_HSYNC

A

AE20

I/O

Horizontal sync

C4

EVENNOTODD

a

AF20

I/O

Vertical sync

C4

a. 5 V tolerant

 7368868E

STMicroelectronics Confidential

37/709

Confidential

Bit 0

SC0_DATAOUT or ASC0_TXD

a

Bit 1

SC0_DATAIN or ASC0_RXD

a

Bit 2

SC0_CG_EXTCLK

Bit 3

SC0CG_CLK or SMCDSS_CLK

b

Bit 4

(SCO_RESET)

Bit 5

(SC0_NOT_SETVCC)

Bit 6

SC0_DIR or ASC0_NOTOE

c

,

(SC0_NOT_SETVPP)

Bit 7

(SC0_DETECT)

a. ASC0 TX/RX data becomes smartcard TX/RX data when the ASC module is used in

smartcard mode.

b. Output function between PIO or smartcard module clock generator alternate function and

clock generator module frequency synthesizer clock is selected by bit 28 in the interconnect
register CONFIG_CONTROL_A (SMCARDA_DSSSMCLK_NOT_PIOBIT3). If the DSS
smartcard mode is selected (bit 28 = 1), this overrides the normal PIO or PIO alternate
function output.

c. When ASC0 is used in nonsmartcard mode, the smartcard direction signal becomes an active

low ASC TX output enable signal. The signals are in fact the same, that is, SC0_DIR = 0
means smartcard TX is active.

Bit 0

SC1_DATAOUT or ASC1_TXD

a

Bit 1

SC1_DATAIN or ASC1_RXD

a

Bit 2

SC1_CG_EXTCLK

Bit 3

SC1CG_CLK or SMCDSS_CLK

b

Bit 4

 (SC1_RESET)

Bit 5

YC[1]

YC[1], (SC1_NOT_SETVCC)

Bit 6

SC1_DIR or ASC1_NOTOE

c

,

(SC1_NOT_SETVPP)

Bit 7

YC[0] (SC1_DETECT)

YC[0]

a. ASC1 TX/RX data becomes smartcard TX/RX data when the ASC module is used in

smartcard mode.

b. Output function between PIO or smartcard module clock generator alternate function and

clock generator module frequency synthesizer clock is selected by bit 29 in the interconnect
register CONFIG_CONTROL_A (SMCARDB_DSSSMCLK_NOT_PIOBIT3). If the DSS
smartcard mode is selected (bit 29 = 1) this overrides the normal PIO or PIO alternate function
output.

c. When ASC1 is used in nonsmartcard mode the smartcard direction signal becomes an active

low ASC TX output enable signal. The signals are in fact the same, that is, SC1_DIR = 0
means smartcard TX is active.

38/709

STMicroelectronics Confidential

  7368868E

Confidential

Bit 0

MAFE_HC1 or NOT_ASC4_RTS

a

Bit 1

MAFE_DOUT or ASC4_TXD

a

Bit 2

MAFE_DIN or ASC4_RXD

a

Bit 3

MAFE_FS or NOT_ASC4_CTS

a

Bit 4

MAFE_SCLK

Bit 5

PWM_CAPTURE0

Bit 6

PWM_COMPARE0

Bit 7

PWM_OUT0

a. Controlled by bit MAFE_OR_UART4_SEL in interconnect register CONFIG_CONTROL_D

(bit 20).

Bit 0

SSC0_MTSR_DIN or SSC0_MRST_DIN

SSC0_MTSR_DOUT or SSC0_MRST_DOUT

a

Bit 1

SSC0_SCLKIN

SSC0_SCLKOUT

Bit 2

SSC1_MTSR_DIN or SSC1_MRST_DIN

SSC1_MTSR_DOUT or SSC1_MRST_DOUT

b

Bit 3

SSC1_SCLK

SSC1_SCLK

Bit 4

NOT_CD_REQ[0] or PCMI_LRCLK

I1284PERILOGICHIGH

Bit 5

Slave mode I1284HOSTLOGICHIGH or
PCMI_DATA

Master mode I1284HOSTLOGICHIGH

Bit 6

NOT_CD_REQ[1] or PCMI_SCLK

I1284INNOTOUT

Bit 7

PWM_OUT1

a. Output function selected by bit 24 in interconnect configuration register

CONFIG_CONTROL_B (COMMS_SSC0_DOUT_MRST_NOTMTSR_MUXSEL)

b. Output function selected by bit 25 in interconnect configuration register

CONFIG_CONTROL_B (COMMS_SSC1_DOUT_MRST_NOTMTSR_MUXSEL)