Sharp LC-32P70E (serv.man10) Service Manual ▷ View online
82
LC-26GA5E
LC-32GA5E
LC-26P70E
LC-32P70E
LC-37P70E
2.5.2. Pin Description (Continued)
Pin information
STV0360
8/66
STMicroelectronics Confidential
7283434C
C
on
fid
en
tia
l
Front end controls
16
AGC1
IO
RF AGC control
Σ∆
4
14
AGC2
IO
IF AGC control
Σ∆
4
17, 60
TEST
Reserved test mode, must be grounded
58
IP0
I
General-purpose input port 0 and ADC input for
RF level monitoring
RF level monitoring
-
45
OP0
IO
General-purpose output port 0
4
43
LOCK/OP1
IO
General-purpose output port 1 or lock indicator
4
42
LOCK/OP2
O
General-purpose output port 2 or lock indicator
4
47
AUX_CLK
IO
Auxiliary clock
8
55
CS0
I
Chip select LSB
-
53
CS1
I
Chip select MSB
-
Power supply
13, 28, 39, 57
VDD
Supply
Digital core supply
22, 35, 44, 52
VDD_3.3
Supply
Digital IO supply
15, 24, 30, 37,
41, 46, 54, 56,
59
41, 46, 54, 56,
59
GND
Ground
1. All inputs are 3.3 V compatible
2. All bidirectional pads are 3.3 V capable
3. All outputs are 3.3 V capable
2. All bidirectional pads are 3.3 V capable
3. All outputs are 3.3 V capable
Table 1: STV0360 pin description
Pin number
Name
Type
Description
Drive (mA)
83
LC-26GA5E
LC-32GA5E
LC-26P70E
LC-32P70E
LC-37P70E
2.6. IC4001 (Sti5516)
2.6.1. Pinning
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Note:
1
NC
(not
connected):
indicates
that
the
pin
has
no
electr
ical
connection,
and
ma
y
be
used
to
route
po
w
er or signals on the PCB
.
2
Do not connect: pin is reser
ved. It ma
y ha
ve an electr
ical connection and m
ust not be used.
14
15
16
17
18
19
20
21
22
23
24
25
26
EMIADDR
[5]
GND
VDDGEN
FSYN
NC
CLK27MA
VDD18
VDD33
GND
Do not connect
GND
GND
GND
GND
A
EMIADDR
[4]
GND
GNDGEN
FSYN
VDD AUDIO FSYN
VDD18
VDD33
GND
GND
VDD18
GND
GND
GND
NO
T_P1284
STR
OBE
B
EMIADDR
[3]
VDD
VPLL
CLK
SPEED
SEL
GND AUDIO FSYN
VDD18
VDD33
GND
GND
GND
GND
GND
P1284 B
USY
NO
T_P1284 A
CK
C
EMIADDR
[2]
GND
GND
A
UXCLK OUT
VDD18
VDD33
GND
GND
GND
GND
NO
T_P1284
A
UT
OFD
P1284 SELECT
P1284
PERR
OR
D
VDD33
NO
T_P1284
SELECTIN
NO
T_P1284 INIT
NO
T_P1284 FA
UL
T
E
P1284 DA
TA[4]
P1284 DA
TA[5]
P1284 DA
TA[6]
P1284 DA
TA[7]
F
GND
P1284 DA
TA[1]
P1284 DA
TA[2]
P1284 DA
TA[3]
G
TSIN2L D
AT
A[5]
TSIN2L D
AT
A[6]
TSIN2L D
AT
A[7]
P1284 DA
TA[0]
H
VDD33
TSIN2L D
AT
A[3]
TSIN2L PA
CKET CLK
TSIN2L D
AT
A[4]
J
GND
TSIN2L D
AT
A[0]
TSIN2L D
AT
A[1]
TSIN2L D
AT
A[2]
K
GND
GND
GND
VDD18
TSIN2L BYTE
CLK
TSIN2L ERR
OR
TSIN2L BYTE
CLKV
ALID
L
GND
GND
GND
TSIN1 DA
TA[4]
TSIN1 DA
TA[5]
TSIN1 DA
TA[6]
TSIN1 DA
TA[7]
M
GND
GND
GND
TSIN1 DA
TA[0]
TSIN1 DA
TA[1]
TSIN1 DA
TA[2]
TSIN1 DA
TA[3]
N
GND
GND
GND
TSIN1 BYTE CLK
TSIN1 PA
CKET CLK
TSIN1 ERR
OR
TSIN1 BYTE
CLKV
ALID
P
GND
GND
GND
VDD18
VDD18
VDD18
VDD18
R
GND
GND
GND
SMIMEM CLKIN
SMID
AT
A
ML
SMID
AT
A
MU
NC
T
NO
T_SMI CAS
NO
T_SMI RAS
NO
T_SMIWE
SMIMEM CLK
OUT
U
VDD33
SMID
AT
A
[15]
NO
T_SMI CS0
NO
T_SMI CS1
V
SMID
AT
A
[11]
SMID
AT
A
[12]
SMID
AT
A
[13]
SMID
AT
A
[14]
W
VDD33
SMID
AT
A
[8]
SMID
AT
A
[9]
SMID
AT
A
[10]
Y
GND
SMID
AT
A
[5]
SMID
AT
A
[6]
SMID
AT
A
[7]
A A
VDD33
SMID
AT
A
[2]
SMID
AT
A
[3]
SMID
AT
A
[4]
A B
GND
SPDIF
VDD18
PIO4[4]
VDD33
PIO5[3]
GND
VDD18
VDD33
SMIADDR
[12]
SMIADDR
[13]
SMID
AT
A
[0]
SMID
AT
A
[1]
A C
DO NO
T
CONNECT
PIO3[5]
PIO4[1]
PIO4[5]
PIO5[1]
PIO5[4]
PIO5[7]
GND
VDD33
SMIADDR
[8]
SMIADDR
[9]
SMIADDR
[10]
SMIADDR
[11]
A D
PCM
D
AT
A[1]
PIO3[7]
PIO4[2]
PIO4[7]
PIO5[2]
PIO5[5]
NO
T_
HSYNC
GND
VDD33
SMIADDR
[4]
SMIADDR
[5]
SMIADDR
[6]
SMIADDR
[7]
A E
DO NO
T
CONNECT
PIO4[0]
PIO4[3]
PIO5[0]
PIO4[6]
PIO5[6]
EVENNO
T
ODD
GND
VDD33
SMIADDR
[0]
SMIADDR
[1]
SMIADDR
[2]
SMIADDR
[3]
A F
Pin list
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Pin list
4.1
Pin-out
The
follo
wing
pages
giv
e
the
allocation
of
pins
to
the
pac
kage
,sho
wn
from
the
top
looking
do
wn.
1
2
3
4
5
6
7
8
9
10
11
12
13
A
EMI
SDRAM
CLK
EMIFLASH
CLK
EMID
AT
A
[14]
EMID
AT
A
[13]
EMID
AT
A
[10]
EMID
AT
A
[7]
EMID
AT
A
[3]
EMID
AT
A
[0]
EMIADDR
[23]
EMIADDR
[19]
EMIADDR
[16]
EMIADDR
[13]
EMIADDR
[9]
B
VDD33
VDD33
EMID
AT
A
[15]
EMID
AT
A
[12]
EMID
AT
A
[9]
EMID
AT
A
[6]
EMID
AT
A
[2]
EMIADDR
[25]
EMIADDR
[22]
EMIADDR
[18]
EMIADDR
[15]
EMIADDR
[12]
EMIADDR
[8]
C
VDD33
VDD33
VDD33
EMID
AT
A
[11]
EMID
AT
A
[8]
EMID
AT
A
[5]
EMID
AT
A
[1]
EMIADDR
[24]
EMIADDR
[21]
EMIADDR
[17]
EMIADDR
[14]
EMIADDR
[11]
EMIADDR
[7]
D
VDD33
VDD33
VDD33
VDD33
VDD33
EMID
AT
A
[4]
GND
VDD33
EMIADDR
[20]
VDD18
VDD33
EMIADDR
[10]
EMIADDR
[6]
E
GND
GND
GND
VDD33
F
GND
GND
GND
VDD33
G
VDD18
VDD18
VDD18
GND
H
NO
T_EMI
A
CKREQ
NC
EMIBOO
T
MODE[0]
VDD18
J
NO
T_EMI CAS
NO
T_EMI RAS
NO
T_EMI
REQGNT
VDD33
K
NO
T_EMI CSD
NO
T_EMI CSC
NO
T_EMI CSB
NO
T_EMI CSA
L
NO
T_EMIBE
[1]
NO
T_EMIBE
[0]
NO
T_EMI CSF
NO
T_EMI CSE
GND
GND
GND
M
NO
T_EMIOE
VDD33
VDD33
VDD33
GND
GND
GND
N
VDD33
EMIRD NO
TWR
NO
T_EMI LBA
EMIW
AIT
NO
T
TREAD
Y
GND
GND
GND
P
DCU
TRIGGER
IN
VDD18
VDD18
VDD18
GND
GND
GND
R
VDD18
VDD18
DCU
TRIGGER
OUT
VDD18
GND
GND
GND
T
INTER RUPT[3]
INTER RUPT[2]
INTER RUPT[1]
INTER RUPT[0]
GND
GND
GND
U
PIO0[1]
PIO0[0]
PIO0[2]
VDD33
V
PIO0[6]
PIO0[5]
PIO0[4]
PIO0[3]
W
PIO1[2]
PIO1[1]
PIO1[0]
PIO0[7]
Y
PIO1[5]
PIO1[4]
PIO1[3]
GND
A A
VSSAA
D
A
C
VDD
AA
D
A
C
VDD
ASA
D
A
C
PIO1[6]
A B
OUTM LEFT
VCCAA
D
A
C
GND
AA
D
A
C
OUTM RIGHT
A C
VCCASA
D
A
C
IREF
OUTP LEFT
OUTP RIGHT
GND
VDD33
TDI
LPCLKIN
SHIELD
V
D
A
C
GND
VD
A
C
YCC
VREFD
A
C
RGB
GND
VD
A
C
RGB
VDD18
A D
VBGFIL
PIO2[1]
PIO2[5]
PIO2[7]
PIO3[6]
PIO3[4]
TMS
LPCLK OSC
VREFD
A
C
YCC
CV
OUT
IREFD
A
C
RGB
BOUT
SCLK
A E
PIO1[7]
PIO2[2]
PIO2[6]
PIO3[1]
PIO3[0]
NO
T_TRST
NO
T_RESET
R
TCVDD
IREFD
A
C
YCC
Y
OUT
GOUT
VDD
VD
A
C
RGB
PCMCLK
A F
PIO2[0]
PIO2[3]
PIO2[4]
PIO3[3]
PIO3[2]
TDO
TCK
NO
T_WDOG RST
OUT
COUT
VDD
VD
A
C
YCC
R
OUT
NC
LRCLK
84
LC-26GA5E
LC-32GA5E
LC-26P70E
LC-32P70E
LC-37P70E
2.6.2. Pin Description
Pin list
STi5516
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4.2
STi5516 pin list
Signal names are prefixed by NOT_ if they are active low; otherwise they are active high.
All signals are only 3.3 V capable unless otherwise indicated as 1.8 V or 5 V tolerant.
All signals are only 3.3 V capable unless otherwise indicated as 1.8 V or 5 V tolerant.
Table 2: I/O load capacitance and DC loading
Pad type
Functional pin
group
group
Maximum load
capacitance (pF)
capacitance (pF)
Drive (mA)
Notes
C4
Others
75
4
S8
SDRAM/EMI
75
8
S8b
SDRAM/EMI
75
8
E8
EMI
(programmable)
(programmable)
35
8
a
a. Typical load, but the maximum is 75 pF
25
6
a
15
4
a
5
2
a
P4
PIO
400
4
Table 3: Analog power supply pins
Pin
Location
Number
Function
VDDVDACRGB
AE12
1
3.3 V power supply for RGB video DAC
VDDVDACYCC
AF10
1
3.3 V power supply for YCC video DAC
GNDVDACRGB
AC12
1
Ground for RGB video DAC
GNDVDACYCC
AC10
1
Ground for YCC video DAC
SHIELDVDAC
AC9
1
Shield ground for 2 x video DACs
IREFDACRGB
AD11
1
RGB video DAC current reference
IREFDACYCC
AE9
1
YCC video DAC current reference
VREFDACRGB
AC11
1
RGB video DAC voltage reference
VREFDACYCC
AD9
1
YCC video DAC voltage reference
VDDVPLL
C15
1
3.3 V power for video PLL
VDDAUDIOFSYN
B17
1
1.8 V dedicated power for low jitter audio clock
frequency synthesizer
frequency synthesizer
GNDAUDIOFSYN
C17
1
Dedicated ground for low jitter audio clock frequency
synthesizer
synthesizer
VDDGENFSYN
A16
1
1.8 V dedicated power for nonaudio clock frequency
synthesizer
synthesizer
GNDGENFSYN
B16
1
Dedicated ground for nonaudio clock frequency
synthesizer
synthesizer
VDDAADAC
AA2
1
3.3 V power for audio DAC
VSSAADAC
AA1
1
Ground for audio DAC command switches
85
LC-26GA5E
LC-32GA5E
LC-26P70E
LC-32P70E
LC-37P70E
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VDDASADAC
AA3
1
3.3 V power for audio DAC substrate
VCCAADAC
AB2
1
3.3 V power for audio DAC command switches
GNDAADAC
AB3
1
Ground for audio DAC
VCCASADAC
AC1
1
3.3 V power for audio DAC command switches
substrate
substrate
IREF
AC2
1
Audio DAC output reference current
VBGFIL
AD1
1
Audio DAC filtered output reference voltage
Table 4: Digital power supply pins
Pin
Location
Number
Function
VDD18
a
24
1.8 V power supply
VDD33
b
35
3.3 V power supply
RTCVDD
AE8
1
Low power controller 1.8 V power supply
GND
c
76
Ground for power supplies
a. A19, B18, B22, C18, D10, D18, G1 to G3, H4, L23, P2 to P4, R1, R2, R4, R23 to R26, AC13,
AC16 and AC21.
b. A20, B1, B2, B19, C1 to C3, C19, D1 to D5, D8, D11, D19, E4, E23, F4, J4, J23, M2 to M4,
N1, U4, V23, Y23, AB23, AC6, AC18, AC22, AD22, AE22 and AF22.
c. A15, A21, A23 to A26, B15, B20, B21, B23 to B25, C20 to C24, D7, D15, D16, D20 to D23,
E1 to E3, F1 to F3, G4, G23, K23, L11 to L16, M11 to M16, N11 to N16, P11 to P16, R11 to
R16, T11 to T16, Y4, AA23, AC5, AC14, AC20, AD21, AE21 and AF21.
R16, T11 to T16, Y4, AA23, AC5, AC14, AC20, AD21, AE21 and AF21.
Table 5: RTC pins
Pin
Location
I/O
Function
LPCLKIN
a
AC8
I
Low power clock input
LPCLKOSC
A
AD8
I/O
Low power clock oscillator
a. 1.8 V tolerant
Table 3: Analog power supply pins
Pin
Location
Number
Function
2.6.2. Pin Description (Continued)
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