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UP-X200

Reference Documents

– 7 –

[Low Battery or the battery compartment lid unlocked while in RUN status]

• Reduces OFF current by suspending the power supply and clock of

an unnecessary device, and setting up a CPU port.

•  Suspension is initiated in the following sequence.

1.

The buzzer sounds.

2.

Gwes Power Off System is called.

Note: The buzzer lets the user know that there is a device malfunction.

At the same time, the buzzer also acts as a warning to the user

not to remove the battery.

5

SW RESETSW Status

Transition to the reset status may be initiated in one of the following
way detailed below.

[Pressing the reset button (physical button)]

•  GPIO reset is generated regardless of whether the application is

in operation.

•  The reset button by default is inhibited by the software setting.

Control of the reset button should be set to enable GPIO resetting.
In order to render the reset button invalid while, for example, the

application is storing files on the flash disk, an API capable of

disabling GPIO resetting should be used as the system API.
GPIO resetting, that has been inhibited once can, when resetting

is executed by a different means, be reset as valid only when
allowed by the system API.

[Resetting by software using the GPIO]

•  This reset function is provided by the system API.

• Resetting by this software is also enabled when the above reset but-

ton is disabled.

*

Normally, pressing the reset button should not happen since this is
necessary only in the event of a software malfunction.
Resetting by software is carried out when software processing is nor-
mal. Thus, unexpected resetting while files are being stored on the
Flash disk or when communication with the server is in process can
be avoided. 

6

Reset Status
HW RESET is generated when the [Power] key and reset button
are pressed simultaneously in the OFF, RUN or IDLE status.
Because this operation is unconditional, HW RESET will be gener-
ated even if the reset button is disabled.

*

In other words, HW RESWET is effected if the [Power] key is
pressed when resetting by software is executed.

7

IDLE Status
The FCS should be used to reduce the CPU power consumption
while the CPU is in IDLE status.
In the RUN status, conditions should be CORE 400MHz (Turbo) or
200MHz (RUN), PXBus 200MHz (CCCR 0x161), and in the IDLE
status, CORE 100MHz, PXBus 50MHz (CCCR 0x0121).
Cases when FCS is not carried out in OEMIdle status

•  Touch or battery voltage detection

• Audio record/play

•  When SD is used

8

Discharge Status
This refers to battery discharge and involves no processing by software.

*

The key values shown above are default values and key changes
may be made by rewriting the registry.

The method of recognition ignores rollover when 2 keys are pressed
simultaneously. Additionally, when 2 keys are pressed simultaneously
and one of the two keys is released, the remaining key being depressed
will be valid only if it is different from the previous valid key and invalid if
the same.

Detection of Low battery:

Upon generation of an interruption, 3 read outs at 10ms
intervals are carried out to confirm that the battery is
active.

Detection of battery
compartment lid:

Upon generation of an interruption, 3 read outs at 10ms
intervals are carried out to confirm that the battery is
active.

Key Matrix Symbol

Virtual Key Code

PC Keyboard Symbol

(Reference)

0

VK_0

0

1

VK_1

1

2

VK_2

2

3

VK_3

3

4

VK_4

4

5

VK_5

5

6

VK_6

6

7

VK_7

7

8

VK_8

8

9

VK_9

9

Enter

VK_RETURN

ENTER

CL

VK_BACK

BS

UP

VK_UP

2

DOWN

VK_DOWN

4

RIGHT

VK_RIGHT

3

LEFT

VK_LEFT

1

TRG1

VK_F11

F11

TRG2

VK_F10

F10

•

VK_MULTIPLY

*

[1] pressed

3

[2] pressed

3

[2] cancelled 

3

[1] cancelled

4

4

4

1

Invalid

Invalid

[1] pressed

3

[2] pressed 

3

[1] cancelled

3

[2] cancelled

4

4

4

1

Invalid

2

[1] pressed

3

[2] pressed

3

[2] cancelled

3

[2] pressed

3

[1] cancelled

4

4

4

4

4

1

Invalid

Invalid

Invalid

2

: Key code which application receives.

UP-X200

System Block Diagram

– 8 –

*

"Fatal" is described in a different section: for details refer to the rele-

vant section.

Hard control: This refers to fatal detection by GPIO interruption as

opposed to voltage detection by software.

Level

Capacity Level

Remaining

Detected Voltage

B/L ON

B/L OFF

Good

100%

-

-

90%

4.02V

4.05V

80%

3.92V

3.95V

70%

3.87V

3.90V

60%

3.79V

3.82V

50%

3.72V

3.75V

40%

3.70V

3.73V

Low

30%

3.68V

3.71V

20%

3.66V

3.69V

Very Low

10%

3.58V

3.61V

Fatal

0%

Hard control (3.40V) Hard control (3.40V)

Intel

Application

Processor

PXA255-400MHz 

CF TYPE

SS WIRELESS

 LAN CARD 

LCD 

TG

LCD

480 x 640 

SD

TOUCH

PANEL

SP

UART 

JTAG 

RTC

18 KEY/   

TRIGGER KEY

USB 

HOST 

TYPE A 

Buzzer 

SDRAM

128MB 

DiskOnChip

64MB 

SHARP

NOR Flash

1MB 

SCOOP2 

HOST BUS 

TOSHIBA

TC6393XB 

GENERAL-

PURPOSE

GA

ZEN0599 

SPI

CODEC 

Wolfson

WM9712L 

AC97 

MI

HP

HS

GPIO

SPI  

PWM 

FUART

Development Only 

UP-X200

System Block Diagram

– 9 –

The UP-X200 is furnished with 4 switching power supply circuits for system use.

•  5V step up voltage circuit for liquid crystal display power supply, USB power supply (synchronous rectification system, switching frequency 1MHz,

automatic PWM-PFM switching)

•  3.3V step down voltage circuit for system use (synchronous rectification system, switching frequency 1MHz, automatic PWM-PFM switching)   

•  3.3V step down voltage circuit for CF/SD card use (synchronous rectification system, switching frequency 1MHz, automatic PWM-PFM switching)   

•  1.3V step down voltage circuit for CPU core use (synchronous rectification system, switching frequency 1MHz, automatic PWM-PFM switching)

Because the battery used by the UP-X200 is a lithium ion 1 cell type, the maximum battery voltage is 4.2V.
Therefore the 5V power supply uses a step up voltage circuit.
The 5V and 1.3V power supplies are controlled by SA_PWR_EN. Operation and output of these power supplies are stopped while the main unit is
OFF. (However, because of the 5V power supply is output from the diode in the IC, approximately 3-4V is output.)
The power supply for cards is controlled by CARD_VCC_ON.
The input side power supply of the 3.3V supply for system use normally runs to a certain extent. Although there is a switch on the output side, this is
controlled so that it is always off when the main unit is off to ensure that no voltage is output to the power supply circuit when the auxiliary battery is
backed up in cases where there is no main battery. This means that the system power supply is approximately 3.1V in the OFF status.
Output from the power supply circuit for system use is supplied to the system either directly or via the regulator.
Except during voltage measurement, the power supply circuit for the auxiliary battery for system backup is normally charging and operating at step up
voltage.
Output uses a 3.3V step up voltage circuit and the charge pump method. Charging uses the CV method with a regulator.

 

 

Auxiliary 
battery

Auxiliary 
battery

 

 

AUD_PWR_ON

(CF G/A) 

LCDC circuit 
power supply

LCDC circuit 
power supply

LCDC circuit 
power supply

Audio circuit 
power supply

Audio circuit 
power supply

SD CARD 

CF CARD 

CARD_VCC_ON 

(CF G/A) 

SA_PWR_EN

(CPU) 

From charging 
circuit

1.3V 

3.3V 

5V 

5V step up 
power supply

 

3.3V step down 
power supply

 

 

 

3.3V 

2.0V 

3.3V 

2.5V 

1.5V 

RTC 

3.3V 

1.3V step down 
power supply

3.3V step down 
power supply

3.3V step up
power supply

Power Supply Name

Switch

(Regulator)

Output

Voltage

Control Signal

OFF

Application

VCC5

IC1201

5V

SA_PWR_EN

3 - 4V

USB/LCD power supply

VCC3

Q1205

3.3V

SA_PWR_EN

3.1V

3.3V power supply for system

CARD_VCC

IC1204

3.3V

CARD_VCC_ON

Dependent on setting

3.3V power supply source for CF/SD cards

VCC_CORE

IC1203

1.3V

SA_PWR_EN

0V

1.3V power supply for CPU core

CF_VCC

Q1301

3.3V

#CVCC3EN

Dependent on setting

3.3V power supply for CF card

SD_VCC

Q1302

3.3V

SD_PWR_ON

Dependent on setting

3.3V power supply for SD card

VCC_AUD1V8

IC1305

2V

AUD_PWR_ON

0V

Power supply for CODEC core

VCC_AUD3V

(none)

3.3V

3.1V

Digital power supply for CODEC

VCC_AMP

IC1302

3.3V

AUD_PWR_ON

0V

Analogue power supply for CODEC

TC6393_2R5V

IC1304

2.5V

SA_PWR_EN

0V

VRAM power supply for LCDC

TC6393_1R5V

IC1307

1.5V

SA_PWR_EN

0V

Core power supply for LCDC

UP-X200

System Block Diagram

– 10 –

In its initial status, the charging IC is ON (soft controlled) and is turned OFF without battery or at a fully charge state.

The charge current design value is 1A max, and uses the CC-CV method.

The UP-X200 features two main batteries in parallel and to increase the discharge ratio of these batteries, a software controlled switch to bypass the
diode is furnished. This switch is software controlled to ensure that the battery with the greater remaining capacity discharges, resulting in a more
equal wear on both batteries.

When set on the charger, this switch ensures that both batteries are off and that power is supplied to the system from the external power supply, sav-
ing wear on the main battery.

TC6393_VCC3

IC1308

3.3V

SA_PWR_EN

0V

I/O power supply for LCDC

VAB

(none)

3.5 - 4.3V

3.5 - 4.3V

Battery/external power supply output (Power supply source)

VCC_LCDP8V

IC601

+8V

LCD8V_PWR_EN

0V

+8V power supply for liquid crystal drive

VCC_LCDN4V

IC602

-4V

LCD8V_PWR_EN

0V

-4V power supply for liquid crystal drive

VCC_LCDN8V

Q601

-8V

LCDN8_PWR_EN

0V

-8V power supply for liquid crystal drive

VCC_LCD5V

Q603

5V

LCD5V_PWR_EN

0V

5V power supply for liquid crystal drive

VCC_LCD3V

IC605

3.3V

LCD3V_PWR_EN

0V

3.3V power supply for liquid crystal drive

Power Supply Name

Switch

(Regulator)

Output

Voltage

Control Signal

OFF

Application

Charging 
terminal  

Charging 
circuit 1

To power supply 
circuit

 

Input from AC adapter

Discharge 
switching signal

 

Charging 
circuit 2