Sharp UP-X200 (serv.man9) Service Manual ▷ View online
UP-X200
Circuit diagram and PWB layout
– 35 –
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
9/17
CF GA (SCOOP)
GND
1
D0
3
2
D0
4
3
D0
5
4
D06
5
D0
7
6
/CE1
7
A1
0
8
/O
E
9
A0
9
10
A0
8
11
A0
7
12
Vc
c
13
A0
6
14
A0
5
15
A0
4
16
A0
3
17
A0
2
18
A0
1
19
A0
0
20
D0
0
21
D0
1
22
D0
2
23
WP/-IOIS16
24
/CD2
25
/CD1
26
D11
27
D12
28
D13
29
D14
30
D15
31
/CE2
32
/VS1
33
/IORD
34
/IOWR
35
/WE
36
RDY/BSY/IREQ
37
Vc
c
38
/CSEL
39
/VS2
40
RESET
41
/WAI
T
42
/INPACK
43
?REG
44
BVD2
45
BVD1
46
D0
8
47
D0
9
48
D10
49
GND
50
CN801
ICM-MA2H-SS52-R13H(JST)
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CA10
CD0
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD1
1
CD1
2
CD1
3
CD1
4
CD1
5
CF_VCC
ࠦࡀࠢ࠲ߩ㔚Ḯㄭߊߦ㈩⟎
VCC3
CF_VCC
SA_D[0..31]
SA_A[0..25]
CD0
CD8
CD1
CD9
CD2
CD8
CD1
CD9
CD2
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CA10
CD10
CD1
5
CD1
4
CD7
CD1
3
CD6
CD1
2
CD5
CD1
1
CD4
CD3
ADD
DATA
CVS2_B
CVS1_B
CCD1_B
CCD2_B
CCD2_B
CIOIS16_B
CBVD1
CBVD2
CREG_ B
CWAIT_B
CRESET
CRDY
CWE_B
CIOWR_B
CIORD_
B
COE_
B
CCE2_B
CCE1_B
CCD1_
B
CCE1_B
CCE2_B
CVS1_B
COE_
B
CIORD_B
CIOWR_
B
CWE_B
CRDY
CVS2_B
CRESET
CWAIT_B
CREG_
B
CBVD2
CBVD1
CIOIS16_B
CCD2_
B
5
1
BR80
1
4*100K(1005)
1
BR80
2
2*470K(1005)
CRDY
CBVD1
CIOIS16_B
CBVD2
CWAIT_
B
CCD1_B
CCD2_B
VCC3
CF_VCC
CF_VCC
2
1
C80
2
OPEN(1005)
2
1
C80
3
OPEN(1005)
CWAIT_
B
CRDY
2
1
C80
7
0.1uF/16V(1005)
F
#CVCC3EN
SA_PSKTSEL
CF_IRQ#
CF_PRDY#
CF_PRDY#
SA_PWE#
SA_OE#
SCOOP_CS5#
SA_PIOW#
SA_PWE#
SA_PIOR#
SA_POE#
SA_PWAIT#
SA_PCE2#
SA_PREG#
SA_IOIS16#
SA_PCE1#
nRESET_IN
CF_IRQ#
CF_PRDY#
CF_PRDY#
SA_PWAIT#
2
1
C804
OPEN(1005)
2
1
C805
OPEN(1005)
2
1
C806
OPEN(1005)
SA_A0
SA_A1
SA_A2
SA_A3
SA_A4
SA_A5
SA_A6
SA_A7
SA_A1
SA_A2
SA_A3
SA_A4
SA_A5
SA_A6
SA_A7
SA_A8
SA_A9
SA_A10
SA_A9
SA_A10
SA_A23
SA_A24
SA_A25
SA_D0
SA_D1
SA_D2
SA_D3
SA_D4
SA_D5
SA_D6
SA_D7
SA_D8
SA_D9
SA_D10
SA_D11
SA_D12
SA_D13
SA_D14
SA_D15
#CVCC3EN
2
1
C80
8
0.1uF/16V(1005)
F
2
1
C80
9
0.1uF/16V(1005)
F
SA_PSKTSEL
CF_IRQ#
CF_PRDY#
SCOOP_CS5#
SA_OE#
SA_PIOW
#
SA_PWE#
SA_POE#
SA_PIOR#
SA_PWAIT#
SA_PCE2#
SA_PREG#
SA_IOIS16#
SA_PCE1#
nRESET_I
N
SA_PSKTSEL
CF_IRQ#
CF_PRDY#
SA_OE#
SCOOP_CS5#
SA_PIOW
#
SA_PWE#
SA_PIOR#
SA_POE#
SA_PWAIT#
SA_PCE2#
SA_PREG#
SA_IOIS16
#
SA_PCE1#
nRESET_I
N
CVPP3EN_B
1
CVPP5EN_B
2
CREV
3
VACT
4
LVDD
5
PD8
7
PD1
8
PD9
9
PD4
14
GND
15
PD12
16
PD5
17
PD13
18
PD6
19
PD14
20
PD7
21
PD15
22
LVDD
23
PA25
24
PA24
25
PA23
26
PA22
27
PA21
28
PA20
29
LVDD
30
PA19
31
PA18
32
PD2
10
PD10
11
PD11
13
PD0
6
PD3
12
PA17
33
PA16
34
PA15
35
PA14
36
GND
37
PA13
38
PA12
39
PA11
40
PA10
41
PA8
43
LVDD
44
PA7
45
PA2
50
PA1
51
PA0
52
GND
53
PSKTSEL2
54
PSKTSEL
55
PRDY
56
PIRQ_B
57
WE_B
58
OE_B
59
CS4_ B
60
PIOW_B
61
PWE_B
62
LVDD
63
PIOR_B
64
POE_B
65
PWAIT_B
66
PCE2_ B
67
PREG_B
68
PA6
46
PA5
47
PA3
49
PA9
42
PA4
48
PIOIS16_B
69
PCE1_ B
70
RESET_B
71
TEST
72
GND
73
CD3
74
CD4
75
CD1
1
76
CD5
77
CD6
79
HVDD
80
CD1
3
81
CA10
86
CCE2_B
87
COE_B
88
CA11
89
GND
90
CIORD_
B
91
CA9
92
CIOWR_B
93
CA8
94
CA17
95
CA13
96
CA18
97
CA14
98
CA19
99
HVDD
10
0
CWE_B
10
1
CA20
10
2
CRDY
10
3
CA21
10
4
CD7
82
CD1
4
83
CD1
5
85
CD1
2
78
CCE1_B
84
CA16
10
5
CA22
10
6
CA15
10
7
GND
10
8
GND
109
CA23
110
CA12
111
CA24
112
CA7
113
CA6
115
CA5
116
HVDD
117
CA2
122
CREG_B
123
CA1
124
CBVD2
125
CA0
126
CBVD1
127
HVDD
128
CD0
129
CD8
130
CD1
131
CD9
132
CD2
133
CD1 0
134
CIOIS16_B(CWP)
135
GND
136
LVDD
137
CCD1_B
138
CCD2_B
139
CVS1_ B
140
CRESET
118
CA4
119
CA3
121
CA25
114
CWAIT_B
120
CVS2_ B
141
CVCCDOWN_B
142
CVCC3EN_B
143
CVCC5EN_B
144
IC80
1
S1L50752F26B0
0
CPU,MEMORY
CPU,MEMORY
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
POWER
RESET
2
1
R80
1
47K(1005)
J
VCC3
CF_VCC
2
1
C810
0.1uF/16V(1005)F
2
1
C811
0.1uF/16V(1005)F
2
1
C812
0.1uF/16V(1005)F
VCC3
2
1
C814
0.1uF/16V(1005)F
2
1
C815
0.1uF/16V(1005)F
2
1
C816
0.1uF/16V(1005)F
2
1
C817
0.1uF/16V(1005)F
CF_VCC
2
1
R80
4
100K(1005)
J
VCC3
AUD_PWR_ON
AUD_PWR_ON
SD_PWR_ON
SD_PWR_ON
BT_PWR_EN
BT_PWR_EN
TP823
N80
1
N80
2
N80
3
N80
4
N80
5
N80
6
N80
7
N80
8
N80
9
N81
0
N81
1
N81
2
N81
3
2
1
R80
5
100K(1005)
J
BT_RESET
CORE_V_SEL
BT_RESET
CORE_V_SEL
SD_BT
SD_BT
POWER
POWER
N815
PWR_SOURCE
CF CARD CN
N817
N81
8
N81
9
N82
0
N821
TP823A
TC6393RST#
TC6393RST#
TC6393XB / TG
N816
CARD_VCC_ON
CARD_VCC_ON
PWR_SOURCE
2
1
C80
1
100uF/6.3V(B2)
UP-X200
Circuit diagram and PWB layout
– 36 –
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
10/17
SD CARD
SD_VCC
2
1
R901
62K(1005)J
2
1
R905
10
K(1005)J
2
1
R90262K(1005)J
2
1
R90362K(1005)J
2
1
R904
62K(1005)J
2
1
R90
6
100(1005)
J
2
1
R907
1
00(1005)
J
2
1
C901
1uF/10V(1608)B
VCC3
SD_W
P
SD_W
P
SD_DET#
SD_DET#
SD_CMD
SD_CS#
SD_CLK
SD_CLK
SD_DAT
SD_DAT
SD_INT#
SD_INT#
2
1
R90
8
62K(1005)
J
2
1
R90
9
62K(1005)
J
SD_CS#
SD_CMD
2
1
C90
2
100pF(1005)
2
1
R910
10(1005)
J
SD_VCC
BT_RXD
BT_CTS#
1
BR901
2*100K(1005)
SD CARD I/F
CPU
CPU
CPU
CPU
CPU
BT_CTS#
BT_RXD
CPU
CPU
CPU
2
1
R911
1M(1005)
J
CPU
IR_RXD
2
1
R914
100K(1005)J
CPU
N90
1
N90
2
N90
3
N90
4
N90
5
N90
6
N90
7
IR_RXD
N921
N922
N916
N914
N915
DATA 3
1
COMMAND
2
VSS
3
VDD
4
CLK
5
VSS
6
DATA 0
7
DATA 1
8
DATA 2
9
DETECT
10
GND
11
GND
13
W/
P
12
HOLD_DOWN
14
CN90
1
SG3S013V1A(JAE)
N93
0
The hold down of the frame is
connected directly with GND
UP-X200
Circuit diagram and PWB layout
– 37 –
SD0
15
SD1
16
SD2
17
SD3
18
SD4
19
SD5
20
SD6
21
SD7
22
SD8
25
SD9
26
SD10
27
SD11
28
SD12
29
SD13
30
SD14
31
SD15
32
SA0
1
SA1
2
SA2
3
SA3
4
SA4
5
SA5
6
SA6
7
SA7
8
SA8
9
SA9
10
SA1
0
11
AEN
12
#C
S
38
#IO
R
35
#IO
W
36
#SBHE
37
RSTDRV
41
#STBY
42
NC
46
#IOIS1
6
45
BLO
14
0
BHO
14
1
IRQ1
47
IRQ2
48
IRQ3
49
IRQ4
50
IRQ5
51
IRQ6
52
IRQ7
53
MSEL
40
#CFG
39
MODE
12
4
TEST1
12
6
TEST2
12
7
TEST3
12
8
TRD
12
9
TW
R
13
2
TO1
13
3
TO2
13
4
TO3
13
5
TO4
13
6
TO5
13
7
TO6
13
8
TO7
13
9
VCC
13
VCC
23
VCC
33
VCC
43
VCC
54
VCC
58
VCC
64
VCC
86
VCC
10
4
VCC
11
7
VCC
12
1
VCC
13
0
VCC
14
3
GND
14
GND
24
GND
34
GND
44
GND
55
GND
59
GND
65
GND
87
GND
105
GND
118
GND
122
GND
131
GND
144
TXD1
66
RTS1
67
DTR1
68
OUT1
1
69
RXD1
70
CTS1
71
DSR1
72
DCD1
73
RI
1
74
TXD2
75
RTS2
76
DTR2
77
OUT1
2
78
RXD2
79
CTS2
80
DSR2
81
DCD2
82
RI
2
83
IRTX2
84
IRRX2
85
TOUT
142
PWM1
56
PWM2
57
DBD
60
SOS
61
PDBD
62
PSOS
63
P20
10
6
P21
10
7
P22
10
8
P23
10
9
PP0
11
0
PP1
11
1
PP2
11
2
PP3
11
3
P10
96
P11
97
P12
98
P13
99
P14
10
0
P15
10
1
P16
10
2
P17
10
3
P0
0
88
P0
1
89
P0
2
90
P0
3
91
P0
4
92
P0
5
93
P0
6
94
P0
7
95
#PTTI
114
PTTO
115
#PTTO
11
6
#RESETOUT
12
3
OSCEN
125
X1
11
9
X2
120
IC100
1
ZEN0599T(TQFP144)
VCC3
SA_D[0..31]
SA_D0
SA_D1
SA_D2
SA_D3
SA_D4
SA_D5
SA_D6
SA_D7
SA_D8
SA_D9
SA_D10
SA_D11
SA_D12
SA_D13
SA_D14
SA_D15
SA_A[0..25]
SA_A1
SA_A2
SA_A3
SA_A4
SA_A5
SA_A6
SA_A7
SA_A8
SA_A9
SA_A10
2
4
Gnd
3
Vc
c
5
Nc
1
IC100
2
TC7S14FU
4
2
1
Gnd
3
Vc
c
5
IC100
3
TC7S32FU
2
1
R100
1
330(1005)
J
2
1
C100
1
100pF(1005)
VCC3
2
1
C100
2
0.1uF/16V(1005)F
SA_PWE#
PXA_SCN_CS2
#
SA_OE#
4
2
1
Gnd
3
Vc
c
5
IC100
4
TC7S32FU
SA_A11
VCC3
2
1
4
Gnd
3
Vc
c
5
IC100
5
TC7S00FU
SCN_IRQ#
GA_STBY#
nRESET_I
N
2
1
C1003
0.1uF/16V(1005)F
VCC3
VCC3
2
1
R1002
100K(1005)J
2
1
R100
3
100K(1005)J
TP100
3
TP100
4
TP100
5
TP100
6
2
1
X100
1
14.7456MHz
2
1
R1007
1M(1005)J
2
1
C1016
3pF(1005)
2
1
C1017
3pF(1005)
VCC3
D
S
G
Q100
1
2SJ30
5
D
S
G
Q100
2
2SJ30
5
4
3
2
1
LED100
1
SML-521MUW
2
1
R100
8
27(2125)J
2
1
R100
9
100(2125)J
VCC3
#BAD_READ
#GOOD_READ
2
1
R1010
0(1005)
PXA_SCN_CS2#
CPU
CPU
CPU
SCN_IRQ#
CPU
CPU
SA_A11
CPU
CPU
GA_STBY#
CPU
nRESET_I
N
SA_PWE#
SA_OE#
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
2
1
C100
4
0.1uF/16V(1005)
F
2
1
C1005
0.1uF/16V(1005)F
2
1
C1006
0.1uF/16V(1005)F
2
1
C1007
0.1uF/16V(1005)F
2
1
C1008
0.1uF/16V(1005)F
2
1
C1009
0.1uF/16V(1005)F
2
1
C1010
0.1uF/16V(1005)F
2
1
C1011
0.1uF/16V(1005)F
2
1
C1012
0.1uF/16V(1005)
F
2
1
C1013
0.1uF/16V(1005)
F
N100
1
N100
2
N100
3
N100
4
2
1
R1011
100K(1005)
J
VCC3
TC6393XB
L3VON
TC6393XB
L3VON
2
1
R1014
OPEN(1005)
VCC3
RESET
BZ_VOL
BZ_VOL
IO_AUDIO
IR_MD0
IR_MD1
FIR_SEL
IR_MD0
IR_MD1
FIR_SEL
SD / BT
SD / BT
SD / BT
N100
5
N100
6
N100
7
N100
8
N100
9
N1010
N1011
N1012
N1013
N1014
N1016
N1018
N1019
TP1020
TP1021
N1022
N1023
HP_L_MUTE
IO_AUDIO
HP_L_MUTE
N1024
SA_PWR_EN
SA_PWR_EN
CPU
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
11/17
I/O
UP-X200
Circuit diagram and PWB layout
– 38 –
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
5
4
3
21
1
2
3
4
5
6
7
8
D
C
B
A
12/17
KEY BO
ARD CONNECT
OR
5
1
BR110
1
4*22K(1005)
5
1
BR110
2
4*1K(1005)
KEY_OUT0
KEY_OUT1
KEY_OUT2
KEY_OUT3
KEY_OUT4
KEY_OUT5
KEY_IN0
KEY_IN1
KEY_IN2
KEY_IN3
TP110
1
TP110
2
TP110
3
TP110
4
TP110
5
TP110
6
TP110
7
TP110
8
TP110
9
TP1110
KEY_OUT6
KEY_OUT0
KEY_OUT1
KEY_OUT2
KEY_OUT3
KEY_OUT4
KEY_OUT5
KEY_OUT6
KEY_IN0
KEY_IN1
KEY_IN2
KEY_IN3
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
ON_BUTTON
ON_BUTTON
RESET
1
BR110
3
2*1K(1005)
1
2
3
4
5
6
7
8
9
10
11
12
CN110
1
FH12-12S-0.5SH
1
1
2
2
CN110
2
BM2B-SRSS(JST)
2
1
R110
1
1K(1005)
J
N110
1
N110
2
N110
3
N110
4
N110
5
N110
6
TP1111
N110
7
TP1112
89
CL
E
nter
4
6
5
7
0
1
2
TRG1
TRG2
KEY_OUT0
KEY_OUT1
KEY_OUT2
KEY_OUT3
KEY_OUT4
KEY_OUT5
KEY_IN0
KEY_IN1
KEY_IN2
KEY_IN3
KEY_IN1
KEY_OUT6
Power
ON_BUTTON
GND
CN1102 Connection place
CN1101 Connection place
Key sheet
3
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