Sharp UP-3500 (serv.man29) Service Manual ▷ View online
UP-3500 (V)
HARDWARE DESCRIPTION
– 27 –
6. POWER SOURCE
AC adapter
19V
3.3V
1.5V
2.5V
1.2V
5V, 5.7V
2.7V
LOW
LOW
QUISCENT
EC31QS06
3.3V (CPU I/O, VDD-CPG, FPGA I/O,
1.8V (LCDC CORE)
other peripheral LOGIC ) MAX 350mA
3.3VB (SRAM, CKDC)
EC31QS06
5V (INVERTER)
20DP : 1A, RS232C* 2ch : 200mA
EC31QS06
1.5V (CPU CORE ) 730mA
2.5V (FPGA VCCAUX ) 50m
1.2V (FPGA VCCINT) 50m
3.6V
BATTERY
19V (DRAWER)
POWER
MONITOR POINT
MONITOR POINT
5.7V
EC31QS06
ON/OFF CONTROLL
BA33DD0T
BA15DD0WHFP
LM2574N+BOOST Tr.
3.3VL(LCDC I/O)
3.3V
ON/OFF CONTROLL
1.8V
UP-3500 (V)
HARDWARE DESCRIPTION
– 28 –
7. RESET
7-1. CIRCUIT COMPOSITION
CK D C X
C KDCR
STOP #
PO FF #
SR ES #
CP U
PTB5
MRESET#
RESET#
TRST#
IR L0#
DONE
HD I_TRST #
FPG A
DONE
PRO G _B
IN IT _ B
R ESE T#
XCF 2 S
POFF #
FL ASH
RESET#
UP-3500 (V)
HARDWARE DESCRIPTION
– 29 –
7-2. OPERATION FLOW
■ Power ON / CKDC reset (Reset switch: Neighborhood of the expansion SRAM socket)
■ Power OFF
8. INTERRUPTION
The interruption is as shown below.
■ CPU port
■ FPGA
For USART, UART, and software interruption, refer to the item of the
FPGA.
POFF# cancel
NO
YES
CKDC sleep
Power ON
CKDC reset
CKDC boot
CKDC system reset cancel
FPGA configuration
FPGA DONE rising
CPU reset cancel
STOP# generates ?
Standby
POF detection
(CKDC,CPU)
YES or when STOP# does not generate for 100ms.
CKDC system reset execution
NO (up to 100ms)
CPU
I/O
External
signal name
Remark
IRL2
I
TOUCH_INT#
TOUCH PANEL INTRRUPT
IRL1
I
FPGAINT#
FPGA INTRRUPTUSART, UART,
CKDC, SOFT INT, LAN, MCR
CKDC, SOFT INT, LAN, MCR
IRL0
I
POFF#
POFF# signal
CMT/CTR3
I
CKDC_SHEN#
SHEN# signal
CMT/CTR3
I
MCRINT#
MCRINT# signal
FPGA
I/O
External
signal name
Remark
EXINT1#
I
KRQ#
CKDC interruption
EXINT2#
I
LANINT#
LAN controller interruption
EXINT3#
I
MCRINT#
MCR interruption
EXINT4#
I
SHEN#
CKDC SHIFT ENABLE
UP-3500 (V)
CIRCUIT DIAGRAM
– 30 –
MODIFIED 07,06,29
modified 07,11,13
modified 07,11,13
MD7
CKDC_SHEN#
PT
B
2
MCRINT
PT
B
4
U1-1_B16
U1-1_B15
U1-1_B14
U1-1_A14
U1-1_A13
U1-1_A14
U1-1_A13
CKDC_HTS
PCLK
U1-1_B16
PSO
U1-1_B15
U1-1_B14
TOUCH_INT#
BACK
A25
A0
A24
BACK
BREQ#
CA
BREQ#
MRESE
T
NMI#
LCDINT#
POFF#
FPGAINT#
MD8
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MD5
MD6
MD4
MD1
MD0
MD8
MD3
RESET
#
CA
NMI#
U1-3_N03
VEPWC
U1-3_N02
U1-3_F18
U1-3_F17
U1-3_N02
U1-3_N03
TOUCH_CS#
LCD-65_G3
LCD-65_G4
LCD-65_R4
LCD-65_R5
LCD-65_R2
LCD-65_R3
LCD-65_G5
LCD-65_R1
LCD-65_B1
LCD-65_B2
LCD-65_G1
LCD-65_G2
LCD-65_B5
LCD-65_G0
LCD-65_B3
LCD-65_B4
LCD-65_HSYNC
LCD-65_DE
LCD-65_DOTCLK
LCD-65_VSYNC
SDDTCT
#
VCPWC
H-UDI_TDO
H-UDI_TDI
H-UDI_TMS
RD#_CAS#
CS0#
CS1#
CS6#
CS4#
CS5#
CS2#
SDRAMCS#
STA
TU
S
1
STA
TU
S
0
STAT
U
S
1
STAT
U
S
0
MD2
SDWP#
SDPOWER#
GPIO_PTK
7
MD7
VEPWC
RYBY#
GPIO_PTK
7
U1-3_F17
TR
S
T
#
ASEBRK#/BRKACK
U1-3_F18
H-UDI_TCK
PT
B
2
PT
B
4
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D31
D30
D29
D28
D3
D2
D1
D0
D27
D26
D25
D24
D23
D22
D21
D20
A21
A20
A19
A18
A17
A16
A15
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A25
A24
A22
A23
RDY#
CKDC_SHEN#
CKDC_STH
CKDC_SCK
MCRINT
A23
TRS
T#
MRES
E
T
SDRXD
9
SDTX
D
9
CKDC_STH
9
CKDC_HTS
9
PSO
9
PCLK
9
CKDC_SCK
9
RESET
#
6
,8,9
LCDINT#
6
TOUCH_INT#
8
FPGAINT#
9
POFF#
2,9
CS4#
3,9
CS5#
3,5
CS2#
3,4
CS1#
3,4
CS0#
3,5
RAS#
3
CKE
3
RD/WR#
3,6
RD#_CAS#
3,6
RESET
#
6
,8,9
H-UDI_TRST#
8
LCD-65_G5
8
LCD-65_R4
8
LCD-65_R2
8
LCD-65_B1
8
LCD-65_G3
8
LCD-65_G1
8
LCD-65_B5
8
LCD-65_B3
8
LCD-65_R1
8
LCD-65_R5
8
LCD-65_R3
8
LCD-65_B2
8
LCD-65_G4
8
LCD-65_G2
8
LCD-65_G0
8
LCD-65_B4
8
A09
SDCLK
9
RDY#
6
LCD-65_DE
8
LCD-65_DOTCLK
8
VCPWC
9
LCD-65_HSYNC
8
LCD-65_VSYNC
8
TOUCH_R
X8
TOUCH_CS#
8
TOU
C
H
_
T
X
8
TOUCH_CLK
8
H-UDI_TDI
8
H-UDI_TDO
8
H-UDI_TMS
8
ASEBRK#/BRKACK
8
H-UDI_TCK
8
BS#
6
DCK
6,9
SDDTCT
#
9
SDPOWER#
9
SDWP#
9
CKIO
3
,6
RYBY#
5
D[0:31]
3,6
A[1:22]
3,4,5,6
SDRAMCS#
3
WE0#_DQM
0
3
,6
WE3#_DQM
3
3
WE2#_DQM
2
3
WE1#_DQM
1
3
,6
CS6#
6
I2C0_SDA
5
I2C0_SCL
5
CKDC_SHEN#
2,9
MCRINT
to SUB
PWB
PWB
9
A23
5
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
SH7760(new
)
U1-2
B01
C01
B10
D05
H18
H17
G19
G20
A17
B17
C16
D17
D16
M19
M20
N19
N20
E03
E04
J04
R18
R17
T18
T17
M03
L04
U15
U13
U09
V15
V13
W13
Y13
W12
Y12
W11
Y11
W10
V09
W09
Y09
W08
Y08
V06
R01
R04
RESET#
RDY#
NMI
MRESET#
MD8
MD7
MD6/IOIS16#
MD5
MD4/CE2B#
MD3/CE2A#
MD2
MD1
MD0
IRL3#
IRL2#
IRL1#
IRL0#
CA
BREQ#
BACK#
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
R34
0
R51
56
BR53-2
86-4
27
2
7
R36
56
R74
10K
BR41-3
68-4
36
3
6
BR36-1
68-4
18
1
8
BR43-2
68-4
27
2
7
BR52
86-4
1
8
2
7
3
6
4
5
BR40-1
68-4
18
1
8
R18
(10K)
BR40-3
68-4
36
3
6
SH7760(new
)
U1-4
Y14
W14
Y07
W07
D10
C10
C12
D12
C15
D08
D06
W06
Y06
W15
D01
P02
N01
K02
Y15
J03
H01
F03
Y10
U06
R02
C08
WE3#/DQM3/ICIOWR#
WE2#/DQM2/ICIORD#
WE1#/DQM1
WE0#/DQM0/REG#
TRST#
TMS
TDO
TDI
TCK
STATUS1
STATUS0
RD/WR#
RD#/CASS#/FRAME#
RAS#
DCK
CS6#
CS5#
CS4#
CS3#
CS2#
CS1#
CS0#
CKIO
CKE
BS#
ASEBRK#/BRKACK
R32
0
R33
56
BR33-8
10K-8
8
9
BR31-1
10K-8
1
16
BR56-2
86-4
27
2
7
BR33-5
10K-8
5
12
BR41-1
68-4
18
1
8
R146
10K
R203
(10K)
R29
0
BR1-6
10K-8
6
11
R86
10K
BR53-1
86-4
18
1
8
R49
1k
BR31-7
10K-8
7
10
R139
(10K)
BR36-4
68-4
45
4
5
BR43-1
68-4
18
1
8
BR55-4
86-4
45
4
5
C56
100pF
R144
10K
BR26-5
10K-8
5
12
BR1-7
10K-8
7
10
R88
10K
BR56-3
86-4
36
3
6
BR39-2
68-4
27
2
7
R19
(10K)
BR32-3
10K-4
3
6
BR36-3
68-4
36
3
6
BR33-1
10K-8
1
16
BR33-6
10K-8
6
11
BR30
10K-4
1
8
2
7
3
6
4
5
BR53-3
86-4
36
3
6
R143
10K
R83
1K
BR1-5
10K-8
5
12
BR36-2
68-4
27
2
7
BR43-3
68-4
36
3
6
R48
86
BR55-2
86-4
27
2
7
R57
56
BR26-7
10K-8
7
10
R47
86
R37
56
BR38-4
68-4
45
4
5
BR56-1
86-4
18
1
8
BR39-1
68-4
18
1
8
BR37-2
68-4
27
2
7
BR1-8
10K-8
8
9
R16
10K
BR31-5
10K-8
5
12
BR26-4
10K-8
4
13
BR37-1
68-4
18
1
8
BR38-3
68-4
36
3
6
C60
330pF
BR37-4
68-4
45
4
5
BR33-3
10K-8
3
14
R89
1K
BR37-3
68-4
36
3
6
BR24-3
10K-8
3
14
SH7760(new)
U1-3
E02
F04
H20
H19
J20
J19
K20
T01
T02
T04
N02
R03
F01
E01
M02
L02
L03
K03
J02
H02
P01
M01
L01
K01
J01
G01
G02
F02
N03
F18
F17
F20
F19
A06
B06
B07
A07
VEPWC/IRQ5#
VCPWC/IRQ4#
RESERVED/AUDSYNC(GPIO:PTK3)
RESERVED/AUDCK(GPIO:PTK4)
RESERVED/AUDATA[3](GPIO:PTK7)
RESERVED/AUDATA[2](GPIO:PTK6)
RESERVED/AUDATA[1](GPIO:PTK5)
MFI-RW/LCD_FLM
MFI-RS/LCD_M_DISP
MFI-MD/LCD_CL2
MFI-INT#/LCD_CLK
MFI-E/LCD_CL1
MFI-D9/LCD_DATA9
MFI-D8/LCD_DATA8
MFI-D7/LCD_DATA7/DRAK3/DACK3
MFI-D6/LCD_DATA6/DREQ3#
MFI-D5/LCD_DATA5/DRAK2/DACK2
MFI-D4/LCD_DATA4/DREQ2#
MFI-D3/LCD_DATA3/IRQ7#
MFI-D2/LCD_DATA2/IRQ6#
MFI-D15/LCD_DATA15
MFI-D14/LCD_DATA14
MFI-D13/LCD_DATA13
MFI-D12/LCD_DATA12
MFI-D11/LCD_DATA11
MFI-D10/LCD_DATA10
MFI-D1/LCD_DATA1
MFI-D0/LCD_DATA0
MFI-CS#/LCD_DON
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
HSPI_TX/SIM_D/MCDAT
HSPI_RX
HSPI_CS#/SIM_RST/MCCMD
HSPI_CLK/SIM_CLK/MCCLK
R151
(10K)
BR55-3
86-4
36
3
6
R95
1K
BR1-4
10K-8
4
13
R5
10K
BR24-2
10K-8
2
15
R40
56
BR38-2
68-4
27
2
7
C59
100pF
R41
56
R52
56
R94
1K
R42
56
BR31-2
10K-8
2
15
BR39-4
68-4
45
4
5
R61
0
R65
56
R38
0
R43
56
R92
10K
R85
10K
BR33-2
10K-8
2
15
R35
56
R44
56
R142
4.7K
BR38-1
68-4
18
1
8
BR1-2
10K-8
2
15
BR24-8
10K-8
8
9
R53
56
R93
10K
BR26-3
10K-8
3
14
BR55-1
86-4
18
1
8
R45
56
R91
10K
BR1-1
10K-8
1
16
R60
56
R56
56
BR26-8
10K-8
8
9
BR24-1
10K-8
1
16
BR32-1
10K-4
18
1
8
C139
0.1uF
3.3V
IC1A
SN74LV08APW
1
2
3
14
7
BR39-3
68-4
36
3
6
BR54-4
86-4
45
4
5
R46
56
BR31-6
10K-8
6
11
BR31-4
10K-8
4
13
R90
1K
R64
86
BR42-3
68-4
36
3
6
R96
1K
C133
0.1uF
R39
10K
R31
10K
R138
10K
BR42-2
68-4
27
2
7
BR54-2
86-4
27
2
7
BR1-3
10K-8
3
14
BR31-8
10K-8
8
9
R87
1K
BR26-6
10K-8
6
11
R72
10K
BR32-2
10K-4
2
7
R55
56
R81
1K
BR42-1
68-4
18
1
8
BR31-3
10K-8
3
14
BR26-2
10K-8
2
15
BR25
10K-4
1
8
2
7
3
6
4
5
R66
56
BR26-1
10K-8
1
16
R30
0
R58
33
R54
56
BR42-4
68-4
45
4
5
BR54-3
86-4
36
3
6
R70
10K
R79
1K
R50
1K
BR28
10K-4
1
8
2
7
3
6
4
5
R62
0
BR24-7
10K-8
7
10
R63
10K
SH7760(new
)
U1-1
A11
A12
A14
A13
A10
B12
B13
B15
B14
B11
A16
B16
A15
U20
V20
W20
U18
W18
Y18
W17
W16
Y16
Y17
V17
U17
Y19
Y20
V19
U19
U01
V01
Y01
Y02
T03
V04
Y04
Y05
W05
W04
Y03
W03
U03
W01
V02
U02
A09
B09
A08
B08
SCIF2_TXD
SCIF2_RXD
SCIF2_RTS#
SCIF2_CTS#
SCIF2_CLK
SCIF1_TXD
SCIF1_RXD
SCIF1_RTS#
SCIF1_CTS#
SCIF1_CLK
SCIF0_TXD
SCIF0_RXD
SCIF0_CLK
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
CMT_CTR3
CMT_CTR2
CMT_CTR1
CMT_CTR0/TCLK
C150
330pF
BR41-2
68-4
27
2
7
R27
0
C151
4700PF
BR53-4
86-4
45
4
5
R10
10K
R17
(10K)
BR32-4
10K-4
4
5
BR33-4
10K-8
4
13
BR33-7
10K-8
7
10
BR43-4
68-4
45
4
5
BR54-1
86-4
18
1
8
BR29
10K-4
1
8
2
7
3
6
4
5
BR40-4
68-4
45
4
5
BR40-2
68-4
27
2
7
BR24-6
10K-8
6
11
BR24-5
10K-8
5
12
BR24-4
10K-8
4
13
R11
10K
R59
0
BR56-4
86-4
45
4
5
BR27
10K-4
1
8
2
7
3
6
4
5
R28
0
R20
(10K)
BR41-4
68-4
45
4
5
2
3
6
4
1
7
8
5
15
14
11
13
16
10
9
12
1
7
8
2
3
6
5
4
16
10
9
15
14
11
12
13
5
6
7
1
2
6
7
4
12
11
10
16
15
11
10
13
1
5
3
4
6
2
4
3
5
3
6
2
3
2
8
4
12
14
11
7
6
15
9
5
2
4
7
8
8
1
3
15
13
10
9
9
16
14
to SUB PWB
to touch panel PWB
to 6.5 LCD
to SUB PWB
to touch panel PWB
to SUB PWB
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
A
B
C
D
876
54
3
21
1
2
3
4
5
6
7
8
D
C
B
A
1/9
CPU-1 B
US/Contr
ol
CHAPTER 8
.
CIRC
UIT DIA
G
R
A
M
1
.CPU PW
B
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