DOWNLOAD Sharp UP-3500 (serv.man29) Service Manual ↓ Size: 19.97 MB | Pages: 62 in PDF or view online for FREE

Name: Sharp UP-3500 (serv.man29)
Brand: Sharp
SKU: 37571
Rating: 4 (1 reviews)

Model: UP-3500 (serv.man29)
Pages: 62
Size: 19.97 MB
Type: PDF
Document: Service Manual
Brand: Sharp
Device: EPOS / UP3500 Hardware Service Manual
File: up-3500-sm29.pdf
Date: 2018-11-20

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UP-3500 (V)
HARDWARE DESCRIPTION
– 19 –
5. CONNECTION DEVICE
5-1. SDRAM (CPU PWB) 
8MB (64Mbit) SAMSUNG K6S643232H-TC/L70 (
×
32)
Used in 32bit connection. 
5-2. FLASH ROM (CPU PWB) /EPROM
(1) FLASH ROM
4MB (32Mbit) SPANSION S29GL032A90TFIR4 (MIRRORBIT 000000h 
side boot sector) is used. The jumper pin and the socket are used to 
switch the FLASH memory (4MB) and the EPROM (1MB 
×
4).
<When IPL>
When the signal (IPL#) from the jumper pin is 1, the FLASH memory is
assigned to the space of H’0000 0000 -H’003F FFFF. When the signal
(IPL#) from the jumper pin is 0, the FLASH memory is assigned to the
space of H’0040 0000-H’007F FFFF.
■ Connection
(2) EPROM
The EPROM PWB is installed to the connector for the UP-I04EF. 
5-3. SRAM
2MB (16Mbit) 48PIN TSOPI 16Mbit 
×
1 pc. 16bit connection
6bit & 8bit access enabled.  Backup is enabled by a battery.
■ External decoder
*When the power is turned OFF, CS1 - 1# and CS1 - 2# are non-active.
■ SRAM connection
5-4. EXPANSION SRAM
4MB (32Mbit) 48PIN TSOPI 16Mbit 
×
2 pcs. 8bit connection 
× 
2 = 16bit 
connection CYPRESS CY62127DV30
16bit & 8bit access enabled. Backup is enabled by a battery. 
■ External decoder
*When the power is turned OFF, CS2-1# and CS2-2# are non-active. 
■ SRAM connection
CPU
SDRAM
CKIO
CLK
CS3#
CS#
CKE
CKE
A12 - A2
A10 - A0
A14
BA1
A13
BA0
RAS#
RAS#
RD/CASS/FRAME
CAS#
RD/WR#
WE#
WE3/DQM3/ICIOWR
DQM3
WE2/DQM2/ICIORD
DQM2
WE1/DQM1
DQM1
WE0/DQM0/REG
DQM0
D31 - D0
DQ31 - 0
CPU
External signal
FLASH
A21 - A1
1
A20 - A0
CS0#, IPL#
FCS#
CE#
RD#
1
OE#
WE1#
1
WE#
D15 - D0
1
D15 - D0
CAN1_TX/AUDATA [1]
PTA2_RYBY#
RY/BY#
PULLUP
WP#
RESET#
RESET#
BYTE#
BYTE#
CPU
EPROM1
EPROM2
EPROM3
EPROM4
A20 - A1
A19 - A0
A19 - A0
A19 - A0
A19 - A0
CS0#, A21, 
IPL#
External
signal :
PCS1# (E#) 
External
signal :
PCS1# (E#) 
External
signal :
PCS2# (E#) 
External
signal :
PCS2# (E#) 
RD#
G#
G#
G#
G#
D15 - D8
—
D7 - D0
—
D7 - D0
D7 - D0
D7 - D0
—
D7 - D0
—
CS1#
0
1
A21
0
CS1 - 1# Active
—
1
CS1 - 2# Active
—
CPU
SRAM1
A20 - A1
A19 - A0
CS1#, A21
CS1 - 1#
RD#
OE#
WE1#
—
WE0#
WE#
D15 - D0
D15 - D0
CS2#
0
1
A22
0
CS2-1# Active
—
1
CS2-2# Active
—
CPU
SRAM1
SRAM2
A21 - A1
A20 - A0
A20 - A0
CS2#, A22
CS2 - 1#
CS2 - 1#
RD#
OE#
OE#
WE1#
—
WE#
WE0#
WE#
—
D15 - D8
—
D7 - D0
D7 - D0
D7 - D0
—

UP-3500 (V)
HARDWARE DESCRIPTION
– 20 –
5-5. LAN CONTROLLER
LAN9118Rev.C is used. 
The MAC address is saved in the EEPROM (93LC46A) .
■ LANC connection
Pin name
(Signal 
name) 
I/O
Pin Number
Function
D [31:16]
IO
21 - 26, 29 - 33, 
36 - 40
Host Data High
D [15:0]
IO
43 - 46, 49 - 53,
56 - 59, 62 - 64
Host Data Low
A [7:1]
I
12 - 18
Address
nRD
I
92
Read strobe
nWR
I
93
Write strobe
nCS
I
94
Chip select
IRQ
O/OD
72
Interrupt
Reserved
-
71, 73, 75, 84
Reserved
SPEED_SEL
I (PU)  74
100M/10M default
FIFO_SEL
I
76
FIFO Select
TPO+
AO
79
Twisted Pair Transmit 
Output, Positive
TPO-
AO
78
Twisted Pair Transmit 
Output, Negative
TPI+
AI
83
Twisted Pair Receive Input, 
Positive
TPI-
AI
82
Twisted Pair Receive Input, 
Negative
EXRES1
AI
87
PHY external bias resistor
EEDIO,
D32/nD16
IO
67
EEPROM Data / 
Data bus width select
nEECS
O
68
EEPROM chip select
EECLK
O
69
EEPROM clock
XTAL1
I
6
25MHz crystal input
XTAL2
O
5
25MHz crystal input
nRESET
I  (PU)  95
Reset
PME
O
70
Wakeup Indicator
LED3/GPOI2
OD/O/I 100
Full duplex indicator
LED2/GPIO1
OD/O/I 99
Link & Activity indicator
LED1/GPIO0
OD/O/I 98
Speed (100M /10M) 
indicator
RBIAS
AI
10
PLL Bias
ATEST
I
9
Test Pin
VREG
P
2
Power source for Internal 
regulator 
VDD_IO
P
20, 28, 35, 42, 
48, 55, 61, 97
I/O Power
GND_IO
P
19, 27, 34, 41, 
47, 54, 60, 96
I/O GND
VDD_A
P
81, 85, 89
Analog Power
VDD_A_RB
P
91
Analog Power, 
Rev.B is NC (OPEN) 
VSS_A
P
77, 80, 86, 88
Analog GND
VSS_A_RB
P
90
Analog GND, 
Rev.B is NC (OPEN) 
VDD_CORE
P
3, 65
Core voltage decoupling
GND_CORE
P
1, 66
Core GND
VDD_PLL
P
7
PLL Power
VSS_PLL
P
4
PLL GND
VDD_REF
P
8
Reference Power
VSS_REF
P
11
Reference GND
Pin name
(Signal 
name) 
I/O
Pin Number
Function

UP-3500 (V)
HARDWARE DESCRIPTION
– 21 –
5-6. LCD
A TFT of 12.1inch (HT121X01-101 made by BOE hydis) is used. 
The first 1MB of the VRAM allows linear access. 
The rests are assigned to four 256KB windows for access.
Pin name(Signal name)
I/O
Function
Connection point
Signal name at connection pint
AB[20:15]
I
Address CPU
A20Å`A15
AB[14:2]
I
Address Address 
bus 
buffer
A14Å`A2
AB1
I
Address CPU
A1
AB0
I
Reserved
GND
GND
DB[15:0]
IO
Data
Data bus buffer
D15-D0
CS#
I
Chip select
CPU
CS6#
M/R#
I
VRAM/Register select
CPU
A21
RD#
I
Read
CPU
RD#_CAS#
RD/WR#
I
Write
CPU
RD/WR#
WE0#
I
Write enable
CPU
WE0#_DQM0
WE1#
IO
Write enable
CPU
WE1#_DQM1
BS#
I
Bus strobe
CPU
BS#
BURST#
I
NC
NC(OPEN)
BDIP#
I
NC
NC(OPEN)
Reserved
-
NC
NC(OPEN)
WAIT#
O
Wait
CPU
RDY#
RESET#
I
Reset
CPU/Reset circuit
RESET#(0
Ω insert)
BUSCLK
I
Bus clock
CPU
CKIO
INT1#
O
Interrupt signal 
CPU
IRL3
FPDAT[17:0]
O
LCD data
LVDS transceiver 
B0-B2,G0-G2,R0-R2,B3-B5,G3-G5,R3-R5
FPFRAME
O
VSYNC
LVDS transceiver 
FP
FPLINE
O
HSYNC
LVDS transceiver 
LP
FPSHIFT
O
Dot clock
LVDS transceiver 
FPSCLK
FPDRDY
O
Data enable
LVDS transceiver 
M_DE
GPIOG4
IO
Pull-down
Pull-down
GPIOG3
IO
Pull-down
Pull-down
GPIOG2
IO
Pull-down
Pull-down
GPIOG1
IO
Pull-down
Pull-down
GPIOG0
IO
Pull-down
Pull-down
MEMA[11:0]
O
VRAM Address 
VRAM(SDRAM)
MEMA[11:0]
MEMBA[1:0]
O
VRAM bank Address 
VRAM(SDRAM)
MEMBA[1:0]
MEMCS#
O
VRAM chip select
VRAM(SDRAM)
MEMCS#
MEMRAS#
O
VRAM RAS
VRAM(SDRAM)
MEMRAS#
MEMCAS#
O
VRAM CAS
VRAM(SDRAM)
MEMCAS#
MEMWE#
O
VRAM write enable
VRAM(SDRAM)
MEMWE#
MEMDQ[15:0]
IO
VRAM data
VRAM(SDRAM)
MEMDQ[15:0]
MEMDQM1
O
VRAM data I/O mask
VRAM(SDRAM)
MEMUDQM
MEMDQM0
O
VRAM data I/O mask
VRAM(SDRAM)
MEMLDQM
MEMCLK
O
VRAM clock
VRAM(SDRAM)
MEMCLK
MEMCKE
O
VRAM clock enable
VRAM(SDRAM)
MEMCKE
GPIOA7
IO
Pull-down
Pull-down
GPIOA6
IO
Pull-down
Pull-down
GPIOA5
IO
Pull-down
Pull-down
GPIOA4
IO
Pull-down
Pull-down
GPIOB7
IO
Pull-down
Pull-down
GPIOB6
IO
Pull-down
Pull-down
GPIOB5
IO
Pull-down
Pull-down
GPIOB4
IO
Pull-down
Pull-down
GPIOC[7:0]
IO
Pull-down
Pull-down
GPIOD3
IO
Pull-down
Pull-down

UP-3500 (V)
HARDWARE DESCRIPTION
– 22 –
Pull-up/Pull-down: 10k
Ω
GPIOD2
IO
Pull-down
Pull-down
GPIOD1
IO
Pull-down
Pull-down
GPIOD0
IO
Pull-down
Pull-down
CNF8
I
PLL1 clock source(=0)
Pull-up/down
Pull-up(NU),Pull-down
CNF7
I
PLL1 clock
 source(=1)(Select: BUS-
CLK)
Pull-up/down
Pull-up,Pull-down(NU)
CNF6
I
HostBus(=0)
Pull-up/down
Pull-up,Pull-down(NU)
CNF5
I
Access method
 (=0)(Select: DirectAc-
cess)
Pull-up/down
Pull-up,Pull-down(NU)
CNF4
I
HostBus(=1)
Pull-up/down
Pull-up,Pull-down(NU)
CNF3
I
HostBus(=1)
Pull-up/down
Pull-up,Pull-down(NU)
CNF2
I
HostBus(=0)
Pull-up/down
Pull-up,Pull-down(NU)
CNF1
I
HostBus(=1)
Pull-up/down
Pull-up,Pull-down(NU)
CNF0
I
H o s t B u s ( = 0 ) ( S e l e c -
tion:SH4 Little Endian:
Active High WAIT# with
tri-state)
Pull-up/down
Pull-up,Pull-down(NU)
OSCI1
I
Crystal oscillator/ Clock
input
CPU/CPU/Pull-up/down
CKIO(0
ΩNU), PTJ1(0Ω insert), Pull-up(NU), Pull-down(NU)
OSCO1
O
Crystal oscillator
Pull-up/down
Pull-up(NU), Pull-down(NU)
OSCI2
I
Crystal oscillator/ Clock
input
Pull-up/down
Pull-up(NU),Pull-down
OSCO2
O
Crystal oscillator
Pull-up/down
Pull-up(NU), Pull-down(NU)
CLKI3
I
Clock input
Pull-up/down
Pull-up(NU),Pull-down
TESTEN
I
Test pin reserved
down
Pull-down(NU)
VCP1
O
Test pin reserved
NU(OPEN)
VCP2
O
Test pin reserved
NU(OPEN)
TCK
I
Test pin reserved
NU(OPEN)
TMS
I
Test pin reserved
NU(OPEN)
TDI
I
Test pin reserved
NU(OPEN)
TDO
O
Test pin reserved
NU(OPEN)
TRST
I
Test pin reserved
NU(OPEN)
COREVDD
P
Core power source
1.8V
1.8V
HVDD1
P
HOST I/F power source
3.3VL
3.3VL
HVDD2
P
LCD I/F power source
3.3VL
3.3VL
HVDD3
P
Camera 1 power source
3.3VL
3.3VL
HVDD4
P
Camera 2/GPIO/Other
power source
3.3VL
3.3VL
HVDD5
P
SDRAM I/F power
 source
3.3VL
3.3VL
VSS
P
Common ground
GND
GND
OSCVDD1
P
OSC1 power source
1.8V
1.8V
OSCVSS1
P
OSC1 power source
GND
GND
OSCVDD2
P
OSC2 power source
1.8V
1.8V
OSCVSS2
P
OSC2 ground
GND
GND
PLLVDD1
P
P L L 1   a n a l o g   p o w e r
source
LCDA3.3V
Analog 3.3V
PLLVSS1
P
PLL1 analog ground
LCDAGND
Analog GND
PLLVDD2
P
P L L 2   a n a l o g   p o w e r
source
LCDA3.3V
Analog 3.3V
PLLVSS2
P
PLL2 analog ground
LCDAGND
Analog GND
Pin name(Signal name)
I/O
Function
Connection point
Signal name at connection pint

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