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Fig. 9-2

Hatched area indicates logic unstable.

When +24V power rises, the signal POFF is forced high (A), by which
time the +5V supply becomes stable. The CKDC6 monitors the state
of POFF while updating the timer/calendar in the low power standby
mode, and when the high state of POFF is detected, the system reset
signal (RESET) is set high (B), by which time the output lines STOP
and SCK of the CPU and MPCA6 have been initialized to high, re-
spectively (C). Thereafter, the CKDC6 sets SHEN active (low) (D) to
notify the CPU of the command/data communication ready state.
One byte data/command can be transferred with eight SCK pulses
(F). When one byte has been transferred with eight SCK pulses, the
CKDC6 sets SHEN high to initiate internal processing. After comple-
tion of the internal processing, when the next byte transfer becomes
ready, the CKDC6 sets SHEN back to a low state to wait for the next
byte transfer (G).
Thereafter, the SHEN and SCK timing described above is repeated to
carry on the communication.

When +24V power drops, POFF goes low (H).
A low on the POFF line causes a low level interrupt request which is
sent the IRQ0 pin of the CPU. Within a maximum of 10msec of the
low level IRQ0 input, the CPU performs software processing neces-
sary for power-off, after which the STOP output is set low (I).
When  STOP goes low, the CKDC6 sets RESET low to reset the
whole system (J). And, the +5V supply is held at 4.75V or higher
voltage, after which the voltage drops to a level that the logic circuit
does not operate.

Strobes ST0 ~ ST3 are decoded on the keyboard by two 74LS138 3-
to-8 decoders to generate 16 strobe signals of S15 ~ S0.
The key matrix consists of 16 strobe lines and 16 returns lines of
KR0A, KR1A, KR2A, KR3A, KR0B, KR1B, KR2B,  and  KR3B.
To minimize interfacing lines between the CKDC6 and the keyboard
unit, two multiplexers (74HC153) are used to multiplex signals by the
timing controlled with the signals KEX0 and KEX1 which are sent to
the CKDC6 on the return lines of KR0 ~ KR3.

Timing ST

Fig. 9-3

The mode switch in provided with a special return line MODR, apart
from the above return lines.
In the same manner, the clerk, paper feed key  (J/R), and receipt
on/off switches use CFSR as the return line.

Fig. 9-4

CKDC6 directly drives the 7-segment display unit and the dot display
is driven via M66004FP.

Fig. 9-5

A

B

C

D

G

I

J

E

F

H

+5V

POFF

RESET

STOP

SHEN

SCK

+24V

12.45ms

778µ S

10µ S 10µ S 10µ S

KR0A

KR3A

KR0B

KR3B

80µ S

ST3

S15

ST2

ST1

ST0

S14

ST0

KEX0

KEX1

KR0~KR3

S//

RES

DSO

DSCK

DCS

+5V

DG0~

DG11

Display

controller

M66004

FP

DDIG

SO2

SCK2

SDISP

SA~SG

DP,ID

G1~10

7SEG-Display

D0~D35

DOT-Display

16

CKDC 6

976µS

15µS

44.8µS

58µS

Gm

SA,SB,SC,SD
SE,SF,SG

DP,ID

Gm+1

976µS x n

– 28 –

Fig. 9-6

The CKDC6 lines are not high voltage resistive ports. Damage may
occur to the CKDC6 if lines are shorted carelessly when using oscillo-
scope probes.

•

Dot matrix tube
A 4-bit binary output signals (ST0-ST3) from CDKC6 are converted
into the digit drive signal (DG0-DG11) in the M66004FP. 

The CKDC6 controls the character segment (5 x 7) and the indicator
of the dot display by using the controller (M66004FP) for dot display
control.

1

M66004FP/Dot display control signal

Signal

name

Contents

Pin/Remark

DSO

Serial data output signal
for M66004FP

C-MOS pin

DSCK

Serial shift clock output
signal for M66004FP

C-MOS pin. 
Requires to be pulled up

DCS

Chip select output signal
for M66004FP

C-MOS pin

Fig. 10-1

+24V:

Printer, solenoid power

+5V:

VCC (Logic power)

VBAT:

Battery charge

–32V:

Display tube power

VF1, VF2:

Display tube power (AC)

VRAM:

Battery back-uped power

VCKDC:

CKDC-4 Back-up power

Fig. 11-1

By switching VIN (+28.8V) by the transistor TR1 within the STR2024,
DC+24V supply is obtained through the LC network. Stable +24V is
obtained by controlling on/off duty of TR1.

ION:

Current when TR1 is on.

IOFF: Current when TR1 is off.

ENST

ST0~ST3

19.1µ s

DGn

"h" th digit

display

DGn+1

Display off

D0~D35

"h" th didit display pattern

(h+1) th didit display pattern

17.2µ s

(h+1) th digit display

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

: Indicator

Noise filter

DC-DC

Converter

circuit

Battery
circuit

VRAMP

+5V

-32V
VF1/VF2

F1

F2

Switching

regulator

(STR2024)

+24V

+

-

~

~

VCKDC

VBAT

VIN

+28.8V

+

4700µ

63V

5

VIN

TR1

Refer-

ence

voltage

circuit

3

2

4

1

L1 220µ H

IOFF

ION
+24V

Load

C2
2200µ F
35V

R2

STR2024

– 29 –

•

In the ER-A460/A470, infra-red data transmission of the optical
communication system is performed. 

System

IRDA

ASK

REMOTE KEYBOARD

Carrier wave

950 nm

900 

∼

 1050 nm

900 

∼

 950 nm

Sub-carrier wave

(16 times of baud rate clock)

500 kHz

±

10%

33 

∼

 40 kHz

Modulation
system

"0": HIGH level
"1": LOW level
Only around the center of the bit cycle
in HIGH level, 3/16 of the bit cycle is
set HIGH, and the rest is set LOW.

Pulse modulation:
The pulse array of data code is
modulated by the AM system.

Pulse modulation:
The pulse array is modulated by data
codes in the PPM system.

Primary modulation:
The sub-carrier waveform is
amplitude-modulated with this pulse
array.

Primary modulation:
The sub-carrier waveform is
amplitude-modulated with this pulse
array.

Secondary modulation:
With the sub-carrier waveform which
was modulated in the primary
modulation, infra-red rays are
amplitude-modulated.

Secondary modulation:
With the sub-carrier waveform which
was modulated in the primary
modulation, infra-red rays are
amplitude-modulated. 

Modulated
waveform

Baud rate

2.4 

∼

 115.2 kbps

9.6 

∼

 57.6 kbps (ZR-5000: 9600 bps)

—

Serial
communication
system

Start-stop synchronization system
Data length: 8bit
Parity:

None

Stop bit:

1

Start-stop synchronization system
Data length: 8bit
Parity:

ODD

Stop bit:

1

—

Transmission
distance

About 0.75m: ECR to ECR
Min. 0.65m

About 0.75m: ECR to ECR
Min. 0.65m

About 1m

500KHz

"0"

"1"

"0"

"1"

16-division

3/16

UART

Reverse
UART

IRDA

ASK

58.5~76.5 ms

108 ms

108 ms

9 ms

4.5 ms

13.5 ms

Leader Code

Custom Code
      8 bits

Custom Code'
      8 bits

Data Code
      8 bits

27 ms

18 ms~36 ms

58.5 ms~76.5 ms

Data Code
      8 bits

9 ms

4.5 ms

13.5 ms

1.125 ms

2.25 ms

0

1

1

0

0

1

9 ms

2.25 ms

11.25 ms

0.56 ms

Time is the value for 455kHz oscillation.

First
 time

Carrier waveform

Carrier frequency.....fc=fosc/12=38 khz

Second time and later 
(Transmitted only when the key is depressed.)

8.77µs

26.3µs

9 ms or 0.56 ms

<Remote keyboard>

0.56 ms

– 30 –

The infra-red signals which was transmitted from the transmission
unit through the air is received by the photo diode, and sent through
the two-system circuit to the MPCA6, where they are modulated and
inputted to the CPU. 

With the IRTX signal from the MPCA6, Q2 is turned on/off to light
LED1, 2. To strengthen the light intensity, two LED’s are used.

PD

Amplifier

Band-pass
filter

Hysteresis
comparator

ASK

AGC
Amplifier

Bypass
filter

Hysteresis
comparator

IRDA
/REMOCON

+5V

R67

R70

IC1A

R69

C49

C61

R51

R52

R53

IRDA
/REMOCON

MPCA6

C45

Q2

R54

R55

R68

PD1

R56

MPCA6

R56

PD1

R56

R57

C46

R58

R68

R59

Q2

C47

R60

C48

R62

R61

C49

R66

R64

R63

R69

R70

R67

IC1B

C50

R65

+5V

ASK

Q2

LED2

LED1

R72

+5V

R71

IRTX

MPCA6

– 31 –