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Name

Type

Description

Host interface, CD-DSP interface, sub-code interface (32-pin)

RESET#

ID

Reset input (active Low). When shifting from the assert state to deassert state,
initialization process of this device is started.
Stand-by input (active Low). When asserting with RESET#, all of output pins and

STANDBY#

ID

bidirectional pins enter the float state, and this device is electrically separated from
periphery. All internal operations are stopped and the power consumption is minimized.
In the stand-by mode, the contents of SDRAM and setup parameter are not retained.

IDLE

O(p.u.)

Idle, Init, or Reset state display output (active High). It enters the active state after
resetting.
Data bus width of the host interface is determined. It can be changed during resetting

HWID

ID

only. The host interface of the device is set to 8 bits at the low level (GNDP) and 16
bits at the high level (VDDP).
When the width is 16 bits (HWID is VDDP), byte order of the host interface data bus

HORD

ID

is determined. It can be changed during resetting only. The device is set to input/
output m.s. byte HD at [15:8] at the low level (GNDP), and m.s. byte at [7:0] at the
high level. When HWID is at the GNDP level, it is connected to GNDP.

HTYPE

ID

Protocol of the host bus is determined. It can be changed during resetting only. The
device is set  to A type at the low level (GNDP) and B type at the high level (VDDP).

HD[7:0]

I/O

8 I.s. of the host data bus. When HWID input is connected to GNDP, only this signal

(HD[7:4])

(r.t.)

is defined  as the host data signal. When HWID is connected to VDDP, it is used as

(HD[3])

(p.u.)

an 8 I.s. line of 16-bit data bus.

(HD[2:1])

(r.t.)

(HD[0])

(p.u.)

HD[11:8]

I/O

When HWID is connected to VDDP, it is used as a data line 11:8 of the 16-bit host

(HD[11])

(p.d.)

data bus.

(HD[10:8])

(r.t.)

When HWID is connected to VDDP, it is used as a data line 15:12 of the 16-bit host

HD[15:12]

I/O(r.t.)

data bus.  When HWID is connected to GNDP, it is used as a the CD-DSP serial input

port pin as defined below.

CDCLK (HD[12])

I

CD-DSP bit clock input

CDDAT (HD[13])

I

CD-DSP data input

CDFRM (HD[14)

I

CD-DSP LR clock (frame) input

CDERR (HD[15])

I

CD-DSP data error input

HA[3:0]

I

Host address input. The address signal specifying the physical address in this device
 is input.

HCS#

I

Host chip select input. Active Low.
Host protocol A type (HTYPE=GNDP): HR/W#. This input determines the direction of

HWR# (HR/W#)

I

the host access.
Host protocol B type (HTYPE=VDDP): HWR#. Host write input (active Low).

HRD# (HDS)

I

Host protocol A type (HTYPE=GNDP): HDS#. Data strobe input (active Low).
Host protocol B type (HTYPE=VDDP): HRD#. Host read input (active Low).

Glossary

I

Input

O

Output

I/O

Bidirectional

AI

Analog input

AO

Analog output

AI/O

Analog bidirectional

ID

Input not synchronized

p.u.

Terminal internally

p.d.

Terminal internally

with PCLK

pulled up

pulled down

r.t.

Retained terminal

Name

Type

Description

Host interface, CD-DSP interface, sub-code interface (32-pin)...continued

Host ready output (active High). Use this signal when the stream is transferred via
the host bus. External pull-up resistor is required. Prior to transfer of each packet (1

HRDY

O(p.d.)

packet: length in CodBurstLen bytes), make sure that this signal is in the active state,

and then bit streams of CodBurstLen byte long or shorter can be written on this device
consecutively.
Interrupt request (active Low). This is deasserted when the host reads the interrupt
status register of this device and also when the host masks or resets the interrupt

HIRQ#

O(p.u.)

using the interrupt mask register.
When HIRQ# is not asserted, it enters the 3-state mode. (External pull-up resistor is
required.)
Host acknowledge output (active Low). When the protocol is A type, the device asserts
this output and notifies the completion of read or write cycle.

HACK#

O(p.u.)

When this signal is not active, it enters the 3-state mode. (External pull-up resistor is
required.) When the protocol is B type, this signal functions as a wait output signal. If
the high-speed host (microcomputer) is used, this signal may not have to be connected.

GPI/O signal (3-pin)

GPIO

I/O(r.t.)

General-purpose bidirectional pin monitored and controlled by the ADP micro code.
After resetting,  this pin is defined as an input. It can be set by using the ADP command.

GPSI

I

General-purpose input monitored by the DVP micro code.

GPSO

O(p.d.)

General-purpose output controlled by the DVP micro code. After resetting, output
from this pin is switched to Low.

PLL signal (5-pin)
GCLK

ID

27,000 MHz clock or crystal input for main processor.

GCLK1

ID

27,000 MHz master clock input for audio. Normally, this must be connected to GCLK.

XO

AO

Output to crystal connected to GCLK. If the crystal is not used for GCLK, nothing
must be connected to XO.

PLLCFG[1:0]

ID

PLL configuration input. It can be changed only during resetting. Normally, both pins
must be connected to GNDP.

Analog video port (7-pin)

CVBS/G/Y

For CVBS, the composite video signal is output.

(DAC A)

AO

For RGB, the G signal is output.
For YUV, the Y signal is output.

Y/R/V

For CVBS, the Y signal is output.

(DAC B)

AO

For RGB, the R signal is output.
For YUV, the V signal is output.

C/B/U

For CVBS, the C signal is output.

(DAC C)

AO

For RGB, the B signal is output.
For YUV, the U signal is output.

CVBS/C

AO

The CVBS or C signal is selected and output.

(DAC D)
RSET

AI

Resistance load for DAC gain adjustment is inserted between GND and DAC.

VREF

AI

Reference voltage for DAC gain adjustment is input.

COSYNC

O(p.d.)

Composite sync output. Effective only when the RGB analog output is selected.
Otherwise, it is fixed to Low.

Digital video port (5-pin)
VCLKx2

I/O(r.t.)

Main video clock input or output. 27,000 MHz.

VCLK

I/O(r.t.)

Divided VCLKx2 signal. Used as a qualifier of data and sync signal.

HSYNC

I/O(r.t.)

Horizontal sync bidirectional signal pin. Its polarity and length are programmable.

VSYNC

I/O(r.t.)

Vertical sync bidirectional signal pin. Its polarity and length are programmable.

FI

I/O(r.t.)

Field identification bidirectional signal pin. Its polarity is programmable.

Name

Type

Description

Digital audio port (8-pin)

AMCLK

I/O(p.u.)

Audio master clock I/O. Sampling frequency can be selected among 384fs, 256fs,

192fs, and 128fs (programmable).

S/PDIF (AOUT[3])

O(p.d.)

S/PDIF transmitter output. It can be connected to DAC as the fourth audio output

(AOUT [3]). After resetting, this pin outputs the low-level signal.

AOUT[2:0]

O(p.d.)

Serial output of PCM stereo audio for DAC. After resetting, this pin outputs the low-

level signal.

AIN

I

Serial input of PCM stereo audio for ADC.

ALRCLK

O(p.d.)

LR clock output of AOUT [4:0] and AIN. The square wave is formed with the sampling

frequency. The LR polarities are programmable.

ABCLK

O(p.d.)

Bit clock output of AOUT [4:0] and AIN. AOUT is output to this clock in the leading

and trailing edges (programmable) and AIN is latched.

DVD-DSP interface (13-pin)

DVDREQ

O(p.d.)

DVD-DSP data request output (polarity programmable).

DVDVALID

I

DVD-DSP data effective input (polarity programmable).

DVDSOS

I

DVD-DSP data sector start input (polarity programmable).

DVDDAT[7:0]

I

DVD-DSP data input bus.

DVDSTRB

ID

DVD-DSP data bit strobe (clock) input. Polarity programmable.

DVDERR

I

DVD-DSP error input. Polarity programmable.

SDRAM interface (35-pin)

RAMDAT [15:0]

I/O(r.t.)

SDRAM bidirectional data bus.

RAMADD [11:0]

O(p.d.)

SDRAM address bus output.

RAMRAS#

O(p.u.)

SDRAM row selection (active Low) output.

RAMCAS#

O(p.u.)

SDRAM column selection (active Low) output.

PCLK

O(p.d.)

SDRAM clock output (same as the internal processing clock).

RAMDQM

O(p.d.)

SDRAM data masking (active High) output.

RAMCS0#

O(p.u.)

SDRAM chip select (active Low) output. Lower 2 Mbyte device.

RAMCS1#

O(p.u.)

SDRAM chip select (active Low) output. Upper 2 Mbyte device.

RAMWE#

O(p.u.)

SDRAM write enable (active Low) output.

TEST signal (pin 3)

SCNENBL

ID

Test pin. Normally connected to GNDP.

TESTMODE

ID

Test pin. Normally connected to GNDP.

ICEMODE

ID

Test pin. Normally connected to VDDP.

Power signal (49-pin)

GNDP

S

Ground for 3.3V digital power supply.

VDDP

S

3.3V digital power supply

VDDIP

S

3.3V digital power supply

GNDAAM

S

Ground for PLL power supply for 3.3V AMCLK generation.

VDDAAM

S

PLL power supply for 3.3V AMCLK generation.

GNDC

S

Ground for 1.8V digital power supply.

VDDC

S

1.8V digital power supply.

GNDA

S

Ground for PLL power supply for 1.8V internal clock generation.

VDDA

S

PLL power supply for 1.8V internal clock generation.

VDDD

S

Analog power supply for 3.3V video DAC.

GNDDAC

S

Ground for Analog power supply for 3.3V video DAC.

[D,B,P,S]

VDDA

STNDBY#

GNDA

RESET#

SCNENBL

VDDP

VCLKx2

GNDP

TESTMODE

VDDAAM

AMCLK

GNDAAM

S/PDIF/AOUT3

GPIO

VDDP

AOUT0
AOUT1
AOUT2

ALRCLK

VDDP

ABCLK

VDDC

GPSO

GNDC

GPSI

GNDP

DVDERR
DVDSOS

DVDVALID

DVDSTRB

DVDREQ

DVDDAT0
DVDDAT1
DVDDAT2
DVDDAT3
DVDDAT4
DVDDAT5
DVDDAT6
DVDDAT7

IDLE

HORD

HWID

VDDP

HTYPE

HD15/CDERR

HD14/CDFRM

HD13/CDDAT

HD12/CDCLK

HD11/TCK

GNDP

HD10/TMS

VDDC

HD9/TDO

GNDC

HD8/TDI

VDDP

HD7

HD6

VDDIP

HD5

HD4

HD3

HD2

HD1

HD0

VDDP

HA3

HA2

HA1

HA0

HWR#/HR/W#

HCS#

VDDC

HRD#/HDS#

GNDC

HRDY

HIRQ#

VDDP

HACK#

GNDP

GNDP
RAMDAT4
RAMDAT11
VDDP
RAMDAT5
RAMDAT10
RAMDAT6
GNDC
RAMDAT9
VDDP
RAMDAT7
GNDP
RAMDAT8
VDDP
PCLK
GNDP
RAMDQM
VDDC
RAMWE#
RAMCAS#
RAMRAS#
RAMCS1#
VDDP
RAMCS0#
GNDP
RAMADD11
RAMADD9
RAMADD10
VDDP
RAMADD8
RAMADD0
GNDP
RAMADD7
RAMADD1
RAMADD6
RAMADD2
VDDP
RAMADD5
RAMADD3
RAMADD4

GCLK

XO

PLLCFG0

GCLK1

VDDC

PLLCFG1

GNDC

AIN

ICEMODE

VREF

GNDDAC_S

GNDDAC_P

RESET

GNDDAC_B

C/B/UDAC_C

Y/R/VDAC_B

VDDD

CVBS/C/DAC_D

CVBS/G/Y/DAC_A

GNDDAC_D

COSYNC

VDDIP

VDDP

GNDP

FI

HSYNC

VDDP

VSYNC

VCLK

RAMDAT0

RAMDAT15

VDDP

RAMDAT1

RAMDAT14

GNDP

RAMDAT2

RAMDAT13

VDDP

RAMDAT3

RAMDAT12

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