Sharp DV-NC60H (serv.man13) Service Manual ▷ View online
62
DV-NC55S/H
DV-NC60H
DV-NC60H
MD
2
V
cc
V
cc
V
cc
V
cc
V
cc
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
PD
7
/D
15
PD
6
/D
14
PD
5
/D
13
PD
4
/D
12
PD
3
/D
11
PD
2
/D
10
PD
1
/D
9
PD
0
/D
8
PE
7
/D
7
PE
6
/D
6
PE
5
/D
5
PE
4
/D
4
PE
3
/D
3
PE
2
/D
2
PE
1
/D
1
PE
0
/D
0
PA
7
/A
23
/IRQ7
PA
6
/A
22
/IRQ6
MD
1
MD
0
PF
7
/Ø
PF
6
/AS
PF
5
/RD
PF
4
/HWR
EXTAL
XTAL
STBY
RES
WDTOVF
NMI
XTAL
STBY
RES
WDTOVF
NMI
PF
3
/LWR
PF
1
/BACK
PF
0
/BREQ
PG
4
/CS0
PG
3
/CS1
PG
2
/CS2
PG
1
/CS3
PG
0
/CAS
P6
7
/CS7/IRQ3
P6
6
/CS6/IRQ2
P6
5
/IRQ1
P6
4
/IRQ0
P6
3
/TEND1
P6
2
/DREQ1
P6
1
/TEND0/CS5
P6
0
/DREQ0/CS4
PF
2
/LCAS/WAIT/BFEQO
Port G
Port 6
Port F
Port 1
Port 2
Port 4
P1
0
/PO8/TIOCA0/DACK0
P1
1
/PO9/TIOCB0/DACK1
P1
2
/PO10/TIOCC0/TCLKA
P1
3
/PO11/TIOCD0/TCLKB
P1
4
/PO12/TIOCA1
P1
5
/PO13/TIOCB1/TCLKC
P1
6
/PO14/TIOCA2
P1
7
/PO15/TIOCB2/TCLKD
P2
0
/PO0/TIOCA3
P2
1
/PO1/TIOCB3
P2
2
/PO2/TIOCC3
P2
3
/PO3/TIOCD3
P2
4
/PO4/TIOCA4
P2
5
/PO5/TIOCB4
P2
6
/PO6/TIOCA5
P2
7
/PO7/TIOCB5
P4
7
/AN7/DA1
P4
6
/AN6/DA0
P4
5
/AN5
P4
4
/AN4
P4
3
/AN3
P4
2
/AN2
P4
1
/AN1
P4
0
/AN0
V
ref
AV
cc
AV
ss
PA
5
/A
21
/IRQ5
PA
4
/A
20
/IRQ4
PA
3
/A
19
PA
2
/A
18
PA
1
/A
17
PA
0
/A
16
PB
7
/A
15
PB
6
/A
14
PB
5
/A
13
PB
4
/A
12
PB
3
/A
11
PB
2
/A
10
PB
1
/A
9
PB
0
/A
8
PC
7
/A
7
PC
6
/A
6
PC
5
/A
5
PC
4
/A
4
PC
3
/A
3
PC
2
/A
2
PC
1
/A
1
PC
0
/A
0
P3
5
/SCK1
P3
4
/SCK0
P3
3
/RxD1
P3
2
/RxD0
P3
1
/TxD1
P3
0
/TxD0
P5
0
P5
1
P5
2
P5
3
/ADTRG
Port E
Port D
Clock oscillator
Interruption
controller
ROM *
RAM
TPU
PPG
A/D converter
D/A converter
SCI
WDT
DMAC
DTC
H8S/2000 CPU
Bass Controller
Peripheral data bus
Peripheral address bus
Internal data bus
Internal addressbus
Port 5
Port 3
Port C
Port B
Port A
12-4. IC504 IX1687GE
MICRO COM.
• Block Diagram
63
DV-NC55S/H
DV-NC60H
DV-NC60H
12-5. IC508 IX1761GE
TRACK BUFFER INTERFACE
Pin No.
Terminal name
I/O
Operation function
1
VDD1
Supply
Digital power supply +3.3V
2
HADR0
Input
CPU Address bus
3
HADR1
Input
CPU Address bus
4
HADR2
Input
CPU Address bus
5
HADR3
Input
CPU Address bus
6
HADR4
Input
CPU Address bus
7
HADR5
Input
CPU Address bus
8
HADR6
Input
CPU Address bus
9
HADR7
Input
CPU Address bus
10
VSS
Supply
Digital GND
11
VDD1
Supply
Digital power supply +3.3V
12
HDAT0
In/Output
CPU Data bus
13
HDAT1
In/Output
CPU Data bus
14
HDAT2
In/Output
CPU Data bus
15
HDAT3
In/Output
CPU Data bus
16
HDAT4
In/Output
CPU Data bus
17
HDAT5
In/Output
CPU Data bus
18
HDAT6
In/Output
CPU Data bus
19
HDAT7
In/Output
CPU Data bus
20
HRD
Input
CPU Read signal
21
HWR
Input
CPU write signal
22
HAS
Input
CPU address strobe
23
HCS1
Input
CPU chip select signal 1 (Track Buffer Operation)
24
HCS2
Input
CPU chip select signal 2 (bus Voltage Transfer)
25
VSS
Supply
Digital GND
26
VDD1
Supply
Digital power supply +3.3V
27
HWAIT
Output
CPU wait signal (Open drain)
28
HINT
Output
CPU interrupt signal (Open drain)
29
VSS
Supply
Digital GND
30
PDO[0]
Output
Output DVD/CDdata
31
PDO[1]
Output
Output DVD/CDdata
32
PDO[2]
Output
Output DVD/CDdata
33
PDO[3]
Output
Output DVD/CDdata
34
PDO[4]
Output
Output DVD/CDdata
35
PDO[5]
Output
Output DVD/CDdata
36
PDO[6]
Output
Output DVD/CDdata
37
PDO[7]
Output
Output DVD/CDdata
38
PDO[8]
Output
Output DVD/CDdata
39
VSS
Supply
Digital GND
40
VDD1
Supply
Digital power supply +3.3V
41
PSYCO
Output
Output data selector sync signal
42
PDRQO
Output
Output data transfer block signal
43
PDCKO
Output
Output data transfer clock
44
VSS
Supply
Digital GND
45
VDD2
Supply
Digital power supply +5V
46
DVDREQ
Input
Request signal input
47
PDCKI
Input
Input data transfer clock
48
PDRQI
Input
Input data transfer block signal
49
PSYCI
Input
Input data selector sync signal
50
VSS
Supply
Digital GND
51
VDD2
Supply
Digital power supply +5V
64
DV-NC55S/H
DV-NC60H
DV-NC60H
Pin No.
Terminal name
I/O
Operation function
52
PDI[8]
Output
Input DVD/CD data
53
PDI[7]
Output
Input DVD/CD data
54
PDI[6]
Output
Input DVD/CD data
55
PDI[5]
Output
Input DVD/CD data
56
PDI[4]
Output
Input DVD/CD data
57
PDI[3]
Output
Input DVD/CD data
58
PDI[2]
Output
Input DVD/CD data
59
PDI[1]
Output
Input DVD/CD data
60
PDI[0]
Output
Input DVD/CD data
61
VSS
Supply
Digital GND
62
VDD1
Supply
Digital power supply +3.3V
63
VSS
Supply
Digital GND
64
VDD2
Supply
Digital power supply +5V
65
5VBUS[7]
In/Output
CPU bus 5V conversion input/output
66
5VBUS[6]
In/Output
CPU bus 5V conversion input/output
67
5VBUS[5]
In/Output
CPU bus 5V conversion input/output
68
5VBUS[4]
In/Output
CPU bus 5V conversion input/output
69
5VBUS[3]
In/Output
CPU bus 5V conversion input/output
70
5VBUS[2]
In/Output
CPU bus 5V conversion input/output
71
5VBUS[1]
In/Output
CPU bus 5V conversion input/output
72
5VBUS[0]
In/Output
CPU bus 5V conversion input/output
73
NC
–
Not Connect
74
NC
–
Not Connect
75
VSS
Supply
Digital GND
76
VDD1
Supply
Digital power supply +3.3V
77
5VBUFO[B]
Output
5V buffer output B
78
5VBUFI[B]
Output
5V buffer input B (3.3V input)
79
5VBUFO[A]
Output
5V buffer output A
80
5VBUFI[A]
Output
5V buffer input A (3.3V input)
81
GPO[3]
Output
General-purpose output terminal (CPU control)
82
GPO[2]
Output
General-purpose output terminal (CPU control)
83
GPO[1]
Output
General-purpose output terminal (CPU control)
84
GPO[0]
Output
General-purpose output terminal (CPU control)
85
VSS
Supply
Digital GND
86
VDD1
Supply
Digital power supply +3.3V
87
LI[1]
Input
Gate Input[1]
88
LI[2]
Input
Gate Input[2]
89
BUFO[C]
Output
Schmitt trigger buffer output C
90
BUFI[C]
Input
Schmitt trigger buffer input C
91
BUFO[B]
Output
Schmitt trigger buffer output B
92
BUFI[B]
Input
Schmitt trigger buffer input B
93
BUFO[A]
Output
Schmitt trigger buffer output A
94
BUFI[A]
Input
Schmitt trigger buffer input A
95
TEST0
Input
Test terminal 0 (Normal: Low, Test: Hi) Function
96
TEST1
Input
Test terminal 1 (Normal: Low, Test: Hi) RAM
97
TEST2
Input
Test terminal 2 (Normal: Low, Test: Hi) Pin
98
NC
–
Not Connect
99
MRST
Input
27MHz Input terminal
100
VSS
Supply
Digital GND
65
DV-NC55S/H
DV-NC60H
DV-NC60H
VSS
PSYCI
PDRQI
PDCKI
DVDREQ
VDD2
VSS
PDCKO
PDRQO
PSYCO
VDD1
VSS
PDO[8]
PDO[7]
PDO[6]
PDO[5]
PDO[4]
PDO[3]
PDO[2]
PDO[1]
PDO[0]
VSS
HINT
HWAIT
VDD1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VDD1
HADR0
HADR1
HADR2
HADR3
HADR4
HADR5
HADR6
HADR7
VSS
VDD1
HDAT0
HDAT1
HDAT2
HDAT3
HDAT4
HDAT5
HDAT6
HDAT7
HRD
HWR
HAS
HCS1
HCS2
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VDD1
5VBUFO[B]
5VBUFI[B]
5VBUFO[A]
5VBUFI[A]
GPO[3]
GPO[2]
GPO[1]
GPO[0]
VSS
VDD1
LI[1]
LI[2]
BUFO[C]
BUFI[C]
BUFO[B]
BUFI[B]
BUFO[A]
BUFI[A]
TEST0
TEST1
TEST2
NC
MRST
VSS
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS
NC
NC
5VBUS[0]
5VBUS[1]
5VBUS[2]
5VBUS[3]
5VBUS[4]
5VBUS[5]
5VBUS[6]
5VBUS[7]
VDD2
VSS
VDD1
VSS
PDI[0]
PDI[1]
PDI[2]
PDI[3]
PDI[4]
PDI[5]
PDI[6]
PDI[7]
PDI[8]
VDD2
IPD
Interface
Host
Interface
RAM
(4.2Kbyte)
Memory
CTL
Error
Detect
ID
Detect
GPO
Interface
OPD
Interface
Timing
Gen.
ZZ
ZZ
ZZ
• Block Diagram
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