Sharp DV-NC60H (serv.man13) Service Manual ▷ View online
70
DV-NC55S/H
DV-NC60H
DV-NC60H
Refresh
Interval Timer
Refresh
Counter
Self Refresh Counter
Address
Register
Register
Burst Length
Counter
Column Addr.
Latch & Counter
512Kx16
Bank 1
Column Decoder
Sense AMP & I/O gates
Column Decoder
Sense AMP & I/O gates
Mode Register
Test Mode
I/O Control
512Kx16
Bank 0
Row Addr. Latch/Predecode
Row Addr. Latch/Predecode
State Machine
Data Input/Output Buffers
Row Decoder
Precharge
Row Active
Column Active
Overflow
Address[0:10]
Audio/Self Refresh
Ref. Addr.[0:11]
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CLK
CKE
BA(A11)
CS
RAS
CAS
WE
UDQM
LDQM
35
CLK
Clock
The system clock input. All other inputs are referenced to the SDRAM on
the rising edge of CLK.
the rising edge of CLK.
34
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh.
be one of the states among power down, suspend or self refresh.
18
CS
Chip Select
Command input enable or mask except CLK, CKE and DOM
19
BA
Bank Address
Select either one of banks during both RAS and CAS activity.
20~24
A0~A10
Address
Row Address: RA0~RA10, Column Address: CA0~CA7
27~32
17, 16, 15
RAS, CAS, WE
Row Address Strobe,
RAS, CAS and WE define the operation.
Column Address Strobe,
Refer function truth table for details.
Write Enable
14, 36
LDQM, UDQM
Data Input/Output Mask
DQM control output buffer in read mode and mask input data in write mode.
2, 3, 5,
I/O0~15
Data Input/Output
Multiplexed data input/output pin
6, 8, 9, 11, 12, 39, 40,
42, 43, 45, 46, 48, 49
42, 43, 45, 46, 48, 49
VDD/VSS
Power Supply/Ground
Power supply for internal circuit and input buffer.
1, 25, 26
4, 7, 10,
VDDO/VSSO
Data Output Power/Ground Power supply for DO
13, 38, 41, 44, 47, 50
33, 37
NC
No Connection
No connection
12-7. IC602-3 IX0751TA 16M SDRAM
Pin No.
Terminal Name
Name
Input Function
• Block Diagram
71
DV-NC55S/H
DV-NC60H
DV-NC60H
Pin No. Terminal Name In/Output
Operation function
3/5V system
Remarks
1
ASLCN
Output
Data slice negative pole output
3V system
Analog output terminal
2
ASLCO
Output
Analog data slice output
3V system
Analog output terminal
(Digital slice output enabled at differential input)
3
DVSS
–
Ground for DAC only
–
4
RO
Output
R-ch output signal
3V system
Analog output terminal
5
DVDD
–
Power supply for DAC only
3V system
6
DVR
Output
Amplifier reference signal output
3V system
Analog input terminal
7
LO
Output
L-ch output signal
3V system
Analog output terminal
8
DVSS
–
Ground for DAC only
–
9
XVSS
–
Ground for oscillator only
–
10
XI
Input
Crystal oscillation input
3V system
Analog input terminal
11
XO
Output
Crystal oscillation output
3V system
Analog output terminal
12
XVDD
–
Power supply for oscillator only
–
13
TESM0
–
Test terminal
3V system
Connected to GND
14
TESM1
–
Test terminal
3V system
OPEN
15
TESM2
–
Test terminal
3V system
Connected to VDD3
16
VDD3
–
3.3V digital power
–
17
VSS3
–
3.3V digital ground
–
18
VPFC
Output
Clock PLL system phase/frequency
3V system
Analog output terminal
comparative output
19
TEST0
Input
Test mode terminal
3V system
Connected to VDD3
20
VLPFI
Input
VCO system filter input for clock PLL
3V system
Analog input terminal
21
VLPFO
Output
VCO system filter output for clock PLL
3V system
Analog output terminal
22
VSS3
–
3.3V digital ground
–
23
MON0
24
MON1
25
MON2
26
MON3
27
MON4
Output
Test monitor
3V system
28
MON5
29
MON6
30
MON7
31
MON8
32
MON9
33
VDD3
–
3.3V digital power
–
34
NC
–
–
35
NC
36
TEST1
Input
Test mode terminal
3V system
Connected to VDD3
37
FLGA
In/Output
General-purpose I/O or flag monitor
5V system
38
FLGB
In/Output
General-purpose I/O or flag monitor
5V system
39
VSS3
–
3.3V digital ground
–
40
/RST
Input
Reset terminal
5V system
Pull-up resistor built in
41
/MA
Input
Microcomputer address enable signal
5V system
Fail-safe terminal
42
/MRD
Input
Microcomputer data read signal
5V system
Fail-safe terminal
43
/MWR
Input
Microcomputer data write signal
5V system
Fail-safe terminal
44
/MCE
Input
Microcomputer chip enable signal
5V system
Fail-safe terminal
45
/MINT
Output
Microcomputer interrupt signal
5V system
Open drain terminal
46
MD0
47
MD1
48
MD2
49
MD3
In/Output
Microcomputer data buss
5V system
50
MD4
51
MD5
52
MD6
53
MD7
54
VDD5
–
5V power supply
–
12-8. IC701 TC94A03F
SERVO/DATA PROCESSOR
72
DV-NC55S/H
DV-NC60H
DV-NC60H
Pin No. Terminal Name In/Output
Operation function
3/5V system
Remarks
55
NC
–
–
56
NC
57
SMCK
Output
22M system clock output
5V system
58
VMCK
Output
Data output system (signal processing
5V system
system) clock output
59
VDD3
–
3.3V digital power supply
–
60
PD0
Output
DVD/CD data output
5V system
61
VSS5
–
5V ground supply
–
62
PD1
63
PD2
Output
DVD/CD data output
5V system
64
PD3
65
PD4
66
VSS3
–
3.3V digital ground
–
67
PD5
68
PD6
Output
DVD/CD data output
5V system
69
PD7
70
PD8
71
/PSYC
Output
DVD data sector sync signal
5V system
72
/PDRQ
Output
DVD data transfer block
5V system
73
PDCK
Output
DVD data transfer block
5V system
74
VDD5
–
5V power supply
–
75
TESM3
–
Test terminal
5V system
Connected to VSS5
76
DIGI
Input
1 bit DAC digital IN input
5V system
77
TESM4
–
Test terminal
5V system
Connected to VDD5
78
VDD3
–
3.3V digital power supply
–
79
BA0
80
BA1
Output
External RAM address output
5V system
81
BA2
82
BA3
83
VSS5
–
5V ground supply
–
84
BA4
85
BA5
86
BA6
Output
External RAM address output
5V system
87
BA7
88
BA8
89
VDD3
–
3.3V digital power supply
–
90
/BOE
Output
External RAM/OE signal
5V system
91
/BRAS
Output
External RAM/RAS signal
5V system
92
/BCAS
Output
External RAM/UCAS signal
5V system
93
/BCASL
Output
External LCAS/WE signal
5V system
94
/BWE
Output
External RAM WE signal
5V system
95
VDD5
–
5V power supply
–
96
BD0
97
BD1
98
BD2
99
BD3
100
BD4
In/Output
External RAM data I/O
5V system
101
BD5
102
BD6
103
BD7
104
BD8
105
VSS3
–
3.3V digital ground
–
106
BD9
107
BD10
In/Output
External RAM data I/O
5V system
108
BD11
109
BD12
110
VSS5
–
5V ground supply
–
73
DV-NC55S/H
DV-NC60H
DV-NC60H
Pin No. Terminal Name In/Output
Operation function
3/5V system
Remarks
111
BD13
112
BD14
In/Output
External RAM data I/O
5V system
113
BD15
114
NC
–
–
115
NC
116
VDD3
–
3.3V digital power supply
–
117
PLCK
In/Output
PLL system clock I/O
3V system
118
TESM5
–
Test terminal
3V system
Connected to GND
119
TESM6
–
Test terminal
3V system
Connected to GND
120
TESM7
–
Test terminal
3V system
OPEN
121
TESM8
–
Test terminal
3V system
OPEN
122
VSS3
–
3.3V digital ground
–
123
CFC1
Output
VCO frequency control signal
3V system
Analog output terminal
124
CFC2
Output
VCO frequency control signal
3V system
Analog output terminal
125
PPW
Output
Phase comparator offset adjustment voltage
3V system
Analog output terminal
output
126
PESV
Input
Phase comparator offset adjustment signal
3V system
Analog input terminal
input
127
PVSS
–
Ground for 3.3V PLL system only
–
128
PESP
Output
Phase comparator offset adjustment signal
3V system
Analog output terminal
output
129
PDOP1
Output
DVD/CD phase control signal
3V system
Analog output terminal
(positive polarity)
130
PDON1
Output
DVD/CD phase control signal
3V system
Analog output terminal
(negative polarity)
131
PDOP2
Output
DVD/CD phase control signal
3V system
Analog output terminal
(positive polarity)
132
PDON2
Output
DVD/CD phase control signal
3V system
Analog output terminal
(negative polarity)
133
LPFN
Input
Data PLL low-pass filter inversion input
3V system
Analog input terminal
134
LPFO
Output
Data PLL low-pass filter output
3V system
Analog output terminal
135
PVREF
–
Reference power supply for data PLL
3V system
system only
136
VCOREF
Input
VCO reference
3V system
Analog input terminal
137
VCOF
Input
VCO self-adjusting filter output
3V system
Analog input terminal
138
PVDD
–
Power supply for 3.3V PLL system only
–
139
RFOn
In/Output
Data slice 6-bit DAC output
3V system
Analog output terminal
(RFOn input enabled at differential input)
140
TESM9
–
Test terminal
3V system
OPEN
141
TEST2
Input
Test mode terminal
3V system
Connected to VDD3
142
RFCD
Input
CD RF signal input
3V system
Analog input terminal
(RFOp input enabled at differential input)
143
RFDVD
Input
DVD RF signal input
3V system
Analog input terminal
(RFOp input enabled at differential input)
144
AVDD
–
Power supply for 3.3V analog system only
–
145
RFCT
Input
RFRP center voltage output
3V system
OPEN
(zero cross import)
146
RFZI
Input
RFRP zero cross signal input
3V system
Analog input terminal
147
TEZI
Input
Tracking error signal input
3V system
Analog input terminal
(zero cross import)
148
AWIN
Input
Active wide PLL control signal input
3V system
Analog input terminal
149
AVSS
–
Ground for 3.3V analog system only
–
150
FEI
Input
Focus error signal input
3V system
Analog input terminal
151
TEI
Input
Tracking error signal input
3V system
Analog input terminal
152
LVL
Input
RF level or sub beam signal add input
3V system
Analog input terminal
153
RFRP
Input
RFRP signal input
3V system
Analog input terminal
154
AVSS
–
Ground for 3.3V analog system only
–
155
TESM10
–
Test terminal
3V system
Connected to VREF
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