Sharp DV-NC60H (serv.man13) Service Manual ▷ View online
74
DV-NC55S/H
DV-NC60H
DV-NC60H
DAC I/F
DAC
1bit DAC
for
CD-DA
Clock
PLL
Micom
I/F
Micom BUS
Servo
Control
DEQ
ADC
Digital Servo
Data
Slicer
PLL
Slice
level
Gen.
Syndrome
operation
ECC
Output
I/F
DRAM
I/F
SYNC Det.
Demodulation
Servo signal
from RFamp
from RFamp
RF signal
from RFamp
from RFamp
to RFamp
to DRAM
to DECORDER
to Micom
Analog
out
Digital
in
to Driver, RFamp
• Block Diagram
Pin No. Terminal Name In/Output
Operation function
3/5V system
Remarks
156
EXTAD
Input
General-purpose external ADC input
3V system
Analog input terminal
157
VREF
–
Reference power supply for analog system
3V system
only: 1.65V
158
FOO
Output
Focus EQ output
3V system
Analog output terminal
159
TRO
Output
Tracking EQ output
3V system
Analog output terminal
160
AVDD
–
Power supply for 3.3V analog system only
–
161
AWCTL
Output
Active wide PLL control output
3V system
Analog output terminal
162
FMO
Output
Feed EQ output
3V system
Analog output terminal
163
DMO
Output
Disc EQ output
3V system
Analog output terminal
164
TEBC
Output
Tracking balance control signal
3V system
Analog output terminal
165
FEBC
Output
Focus balance control signal
3V system
Analog output terminal
166
DPDC
Output
DPD error signal/pit depth adjustment signal 3V system
Analog output terminal
167
EQBC
Output
RF wide boost adjustment signal
3V system
Analog output terminal
168
ANMON
Output
General-purpose PWM output
3V system
Analog output terminal
169
/DFCT
Output
Black dot detection signal
3V system
170
VRCK
Output
RF EQ property control clock
3V system
171
VSS3
–
3.3V digital ground
–
172
SCD
Output
Head amplifier serial data
173
SCL
Output
Head amplifier serial data latch pulse
3V system
174
SCB
Output
Head amplifier serial data clock
3V system
175
FGIN
Input
Disc FG signal input
3V system
Feedback resistor
(with self-bias circuit)
Analog input terminal
176
ASLCP
Output
Data slice positive pole output
3V system
Analog output terminal
Note) Terminals with "/" at the beginning of their names are active "L" ones.
75
DV-NC55S/H
DV-NC60H
DV-NC60H
RAS clock
generator
CAS clock
generator
WE clock
generator
Data I/O Bus
Column decoders
Sense amplifiers
Refresh
counter
Address buffers
and predecoders
Row
decoders
Memory
array
OE clock
generator
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O
Buffer
9
Y
0
-Y
8
X
0
-X
8
512
512 16
OE
WE
UCAS
LCAS
RAS
V
CC
V
SS
A0
A1
A1
A7
A8
A8
12-9. IC702 IX3420CE
4M EDO DRAM
Terminal
Terminal name
Function
16-19, 22-26
A
0
-A
8
Address inputs.
14
RAS
Row address strobe.
28
UCAS
Column address strobe/upper byte control.
29
LCAS
Column address strobe/lower byte control.
13
WE
Write enable.
27
OE
Output enable.
2-5, 7-10
DQ
1
-DQ
16
Data inputs/outputs.
31-34, 36-39
1, 6, 20
V
CC
+3.3V power supply.
21, 35, 40
V
SS
0V ground.
11-12, 15, 30
NC
No connection.
• Block Diagram
76
DV-NC55S/H
DV-NC60H
DV-NC60H
Serial
Data
Interface
Control
Segment
Driver/
Grid
Driver/
Key Scan
Output
Grid
Driver
Dimming Circuit
Timing Generator
Key Matrix Memory
Display Memory
(16bits x 11 Words)
OSC
General
Input
Register
LED
Driver
10 11 12 13
14, 38 7, 43
27
VDD
GND
VEE
K1 K2 K3 K4
SW1
SW2
SW3
SW4
LED1
LED2
LED3
LED4
1
6
5
8
9
42
41
40
39
2
3
4
OSC
VDD
R
DIN
DOUT
CLK
STB
44
15
16
17
18
19
20
21
22
23
24
25
26
28
29
30
31
37
36
35
36
35
34
33
32
32
GR1
GR2
GR3
GR4
GR5
GR6
SG12/GR11
SG13/GR10
SG14/GR9
SG15/GR8
SG16/GR7
SG1/KS1
SG2/KS2
SG3/KS3
SG4/KS4
SG5/KS5
SG6/KS6
SG7
SG8
SG9
SG10
SG11
Pin No.
Terminal name
I/O
Operation function
1-4
SW1 to SW4
I
General purpose input pins
5
DOUT
O
Data output pin (N-Channel, Open-Drain)
This pin outputs serial data at the falling edge of the shift clock (starting from the lower bit).
This pin outputs serial data at the falling edge of the shift clock (starting from the lower bit).
6
DIN
I
Data input pin
This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit)
This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit)
7, 43
GND
–
Ground pin
8
CLK
I
Clock input pin
This pin reads serial data at the rising edge and outputs data at the falling edge.
This pin reads serial data at the rising edge and outputs data at the falling edge.
9
STB
I
Serial interface strobe pin
The data input after the STB has fallen is processed as a command.
When this pin is "HIGH", CLK is ignored.
The data input after the STB has fallen is processed as a command.
When this pin is "HIGH", CLK is ignored.
10-13
K1 to K4
I
Key data input pins
The data inputted to these pins are latched at the end of the display cycle.
The data inputted to these pins are latched at the end of the display cycle.
14, 38
VDD
–
Logic power supply
15-20
SG1/KS1 to
O
High-voltage segment output pins also acts as the key source
SG6/KS6
21-25
SG7 to SG11
O
High voltage segment output pin
26, 28-31
SG12/GR11
High voltage segment/grid output pins
SG13/GR10 to
O
SG16/GR7
27
VEE
–
Pull-down level
32-37
GR6 to GR1
O
High-voltage grid output pins
42-39
LED1 to LED4
O
LED output pin
44
OSC
I
Osillator input pin
A resistor is connected to this pin to determine the oscillation frequency.
A resistor is connected to this pin to determine the oscillation frequency.
12-10. IC5001 PT6312LQ FL DRIVER
• Block Diagram
77
DV-NC55S/H
DV-NC60H
DV-NC60H
BCK
LRCK
NA
NA
SCLK
DATA
TEST1
TEST2
RST
ML
MC
MDI
MDO
Sirial
I/F
Mulcher Level
Data-Sigma
Modulator
DAC
DAC
CR LPF
+
Output Amp
CR LPF
+
Output Amp
V
OUT
L
V
OUT
R
V
COM
L
V
COM
R
V
CC
R
V
CC
L
V
CC
V
DD
CLKO
ZEROL
ZEROR
DGND
AGND
AGNDL
A
GNDR
Power Supply.
x8 (x4)
Oversampling
Dijital Filter
+
Mulcher
Function
Controller
Zero detection
System Clock
Clock
Manager
Function
Control
Pin No.
Terminal name
I/O
Operation function
1
LRCK
I
LRCK clock input (fs)
(1)
2
DATA
I
Audio • Data input
(1)
3
BCK
I
Bit clock input for data.
(1)
4
CLKO
O
System clock buffered output.
5
SCLK
I
System clock input.
6
DGND
–
Digital ground.
7
V
DD
–
Digital power supply +3.3V
8
TEST1
I
Test pin
(2)
(Open or ground)
9
TEST2
I
Test pin
(2)
(Open or ground)
10
V
CC
R
–
Rch, Analog power supply +5V
11
AGNDR
–
Analog ground, Rch
12
V
COM
R
–
Rch Analog output amp. • common
13
V
OUT
R
O
Rch Analog voltage output.
14
AGND
–
Analog • ground
15
V
CC
–
Analog power supply +5V
16
V
OUT
L
O
Lch Analog voltage output
17
V
COM
L
–
Lch Analog output amp • common
18
AGNDL
–
Analog ground, Lch
19
V
CC
L
–
Lch, Analog power supply +5V
20
NA
I
Not connected.
21
NA
I
Not connected.
22
RST
I
Reset
23
ZEROL
O
Lch, Zero data • flug
24
ZEROR
O
Rch, Zero data • flug
25
MDO
O
Mode control, data output
(3)
26
MDI
I
Mode control, data input
(2)
27
MC
I
Mode clock
(2)
28
ML
I
Mode latch
(2)
Note: (1) Schmidt trigger input, 5V logic input possible. (2) Schmidt trigger input pull-down resistor. 5V logic input possible. (3) Try state output
12-11. IC6001 PCM1737 AUDIO DAC
• Block Diagram
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