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HT-CN410DVH

61

IC502 & IC504, Power Half Bridge (STA518)

Table 2. Functional Pin Status

Note:   1.The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.

2.To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) to implemented single BTL (MONO MODE) operation

for high current.

Pin Connection

FAULT

27

0

Fault detected (Short circuit, or Thermal)

FAULT*

27

1

Normal Operation

TRI-STATE

26

0

All powers in Hi-Z state

TRI-STATE

26

1

Normal Operation

PWRDN

25

0

Low consumption

PWRDN

25

1

Normal Operation

THWAR

28

0

Temperature of the IC=130C

THWAR(1)

28

1

Normal Operation

CONFIG

24

0

Normal Operation

CONFIG(2)

24

1

OUT1A=OUT1B ; OUT2A=OUT2B (IF IN1A=IN1B ; IN2A=IN2B)

GND-SUB

OUT2B

OUT2B

V

CC

2B

GND1B

V

CC

1A

GND1A

OUT1A

OUT1A

GND-Reg

VDD

VDD

CONFIG

V

SS

V

SS

V

CC

Sign

V

CC

Sign

18

16

17

15

6

5

4

3

2

21

22

31

32

33

35

34

36

20

1

19

N.C.

GND-Clean

D01AU1273

OUT1B

V

CC

1B

OUT1B

PWRDN

FAULT

TRI-STATE

9

8

7

28

29

30

OUT2A

TH_WAR

10

27

GND2B

OUT2A

V

CC

2A

IN1A

IN2B

IN1B

14

12

11

23

25

26

GND2A

IN2A

13

24

VL

HT-CN410DVH

 62

IC301, IC401, IC5001 Dual Wide Bandwidth Operational Amplifiers (RC4558)

IC302, Channel Multiplexer (D4052BM)

Pin Configuration:

Pin Description:

Pin No.

Function

1

Output A

2

Input A

3

Input A

4

Vee

5

Input B

6

Input B

7

Output B

8

Vcc

1

8

V

DD

IN/OUT

Pin Configuration:

Block Diagram:

IN/OUT

IN/OUT

IN/OUT

OUT/IN

OUT/IN

TOP VIEW

2x

0

Y

2

Y

3

Y

1

Y

INH

V

EE

V

SS

Y

1x

0x

3x

A

B

x

16

1

2

3

4

5

6

8

7

15

14

13

12

11

10

9

D4052BM

3

3

11 15 14 12

13

3

2

2

1

1

0

0

4

2

5

1

X CHANNELS IN/OUT

Y CHANNELS IN/OUT

COMMON Y

OUT/IN

COMMON X
OUT/IN

TG

TG

TG

TG

TG

TG

TG

TG

V

DD

V

EE

V

SS

16

7

8

9

10

6

A

B

INH

LOGIC
LEVEL

CONVERSION

BINARY

TO

1 OF 4

DECODER

WITH

INHIBIT

HT-CN410DVH

63

IC251, VFD Driver (TP6311)

Pin Configuration:

Block Diagram:

SW1

OSC

GND

LED1

LED2

LED3

LED4

LED5

VDD

GR1

GR2

GR3

GR4

GR5

GR6

GR7

GR8

SG20/GR9

SG19/GR10

VEE

VDD

SG18/GR11

SG17/GR12

SG16/GR13

SG15/GR14

SG14/GR15

SG13/GR16

VDD

SG1/KS1

SG2/KS2

SG3/KS3

SG4/KS4

SG5/KS5

SG6/KS6

SG7/KS7

SG8/KS8

SG9/KS9

SG10/KS10

SG1

1/KS1

1

SG12/KS12

SW2

SW3

SW4

DOUT

DIN

NC

CLK

K1

STB

K2

K3

K4

1

2

3

4

5

6

7

8

9

10

11

12

13

39

38

37

36

35

34

33

32

31

30

29

28

27

41 40

42

43

44

45

46

47

48

49

50

51

52

25

26

24

23

22

21

20

19

18

17

16

15

14

LED

DRIVER

OSC

Serial

Data

Interface

Control

Segment

Driver/

Grid

Driver/

Key Scan/

Output

Timing Generator

Display Memory

(20 bits X 16 words)

Key Matrix Memory

Dimming Circuit

Grid

Driver

General

Input

Register

K1 K2 K3 K4

VDD

GND

VEE

VDD

OSC

SW1

SW2
SW3

SW4

LED1

LED2
LED3
LED4
LED5

DIN

DOUT

CLK

STB

R

SG1/KS1
SG2/KS2
SG3/KS3
SG4/KS4
SG5/KS5
SG6/KS6
SG7/KS7
SG8/KS8
SG9/KS9
SG10/KS10
SG11/KS11
SG12/KS12
SG13/GR16
SG14/GR15
SG15/GR14
SG16/GR13
SG17/GR12
SG18/GR11
SG19/GR10
SG20/GR9

GR1
GR2
GR3
GR4
GR5
GR6
GR7
GR8

HT-CN410DVH

 64

IC251, VFD Driver (PT6311)

Pin Description:

SW1 to SW4

I

General Purpose Input pins

1 to 4

DOUT

O

Data Output Pin (N-Channel, Open-Drain) 
This pin outputs serial data at the falling edge of the shift clock (starting from the 
lower bit)

5

DIN

I

Data Input Pin 
This pin inputs serial data at the rising edge of the shift clock 
(starting from the lower bit) 

6

NC

-

No Connection

7

CLK

I

Clock  Input pin
This pin reads serial data at the rising edge and 
outputs data at the falling edge.

8

STB

I

Serial Interface Strobe pin
The data input after the STB has fallen is
processed as a command.
When this pin is “HIGH”, CLK is ignored.

9

K1 to K4

I

Key Data Input Pins
The data inputted to these pins are latched at
the end of the display cycle.

10 to 13

VDD

-

Logic Power Supply

14, 33, 45

SG1/KS1 to SG12/KS12

O

High-Voltage Segment Output Pins
Also acts as the Key Source

15 to 26

SG20/GR9 to SG19/GR10

SG18/GR11 to SG13/GR16

O

High Voltage Segment / Grid Output Pins

36 to 35
32 to 27

VEE

-

Pull-Down Level

34

GR1 to GR8

O

High- Voltage Grid Output Pins

44 to 37

LED1 to LED5

O

LED Output Pin

50 to 46

GND

-

Ground Pin

51

OSC

I

Oscillator Input Pin
A resistor is connected to this pin to determine
the oscillation frequency

52