Sharp HT-CN410DVH (serv.man2) Service Manual ▷ View online
HT-CN410DVH
45
IC207, High Speed Flash Memory (MX29LV160BBTC-70G)
Pin Description:
Pin Configuration:
SYMBOL PIN NAME
A0~A19
A0~A19
Address Input
Q0~Q14
Data Input/Output
Q15/A-1
Q15(Word mode)/LSB addr(Byte mode)
CE
Chip Enable Input
WE
Write Enable Input
BYTE
Word/Byte Selection input
RESET
Hardware Reset Pin/Sector Protect Unlock
OE
Output Enable Input
RY/BY
Ready/Busy Output
VCC
Power Supply Pin (2.7V~3.6V)
GND
Ground Pin
A15
A14
A13
A12
A11
A10
A14
A13
A12
A11
A10
A9
A8
A8
A19
NC
WE
RESET
NC
NC
NC
RY/BY
A18
A17
A17
A7
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29LV160BBTC-70G
HT-CN410DVH
46
IC207, High Speed Flash Memory (MX29LV160BBTC-70G)
Block Diagram:
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y
-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15/A-1
A0-A19
CE
OE
WE
RESET
HT-CN410DVH
47
IC205, HEX Inverters (74HCT04)
Logic Diagram (Positive Logic):
IC202, Wide-Band Video Switch (TS5V330DBQR)
Pin Configuration: Pin Description:
D, DBQ OR PW PACKAGE (TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1Y
2A
2Y
3A
3Y
GND
V CC
6A
6Y
5A
5Y
4A
4Y
SN74HCT04...D, N, OR PW PACKAGE
SN54HCT04...JORW PACKAGE
(TOP VIEW)
A
Y
IN
S1
A
S1, S2
D
IN
S2
A
S1
B
S2
B
D
A
GND
D
B
V
CC
S1
D
D
D
S1
C
S2
D
S2
C
D
C
EN
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Pin Name
Description
Analog Video I/OS
Select Input
Switch - Enable Input
I/OS
S1, S2
D
IN
V
CC
S1
D
D
D
S1
C
S2
D
S2
C
D
C
EN
EN
16
15
14
13
12
11
10
9
Pin Name
Description
Analog Video I/OS
Select Input
Switch - Enable Input
I/OS
IN
S1
A
S1, S2
D
IN
S2
A
S1
B
S2
B
D
A
GND
D
B
V
CC
S1
D
D
D
S1
C
S2
D
S2
C
D
C
EN
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Pin Name
Description
Analog Video I/OS
Select Input
Switch - Enable Input
I/OS
HT-CN410DVH
48
IC201, Programmable Multimedia and DSP Processor (ES6809FADF)
ES6809 Pinout Diagram:
The device pinout for the ES6809 is shown in Figure 1.
AVSS
SLV
DMO
FOO
SLO
RPBC
TRO
NC
TEBC
REFD
IN_M
IN
AVDD3
AVSS
DVCC
IP1
IDSEL
AMPSTBY
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
11
9
11
8
11
7
11
6
11
5
11
4
11
3
11
2
111
11
0
109
108
107
106
105
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
104
103
102
101
100
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
FGIN
CLOSESW
HOMESW
HOMESW
CLOSE
OPENSW
OPEN
MDET
MDET
VD33
VSS
AUX7
EAUX1
AUX3[6]/CAMIN6
EAUX0/CAM_CLK
PCKLQSCN/AUX4[1]
EAUX2/PCLK2XSCN/AUX4[0]
VSYNC#/AUX1[7]
HSYNC#/AUX1[6]
XI
XO
CLK
VSS
VSS
VD33
AUX3[4]/CAMIN4
AUX3[1]/CAMIN1
AUX3[3]/CAMIN3
AUX3[1]/CAMIN1
AUX3[3]/CAMIN3
VSS
VDD
AUX3[2]/CAMIN2
AUX5
AUX4
AUX6
AUX2
AUX4
AUX6
AUX2
VSS
AUX3[7]/CAMIN7
VD33
AUX0
AUX3
RESET#
AUX1
DMA4
DMA5
DMA6
DMA7
VSS
VD33
DMA8
DMA9
DMA3
DMA2
DMA1
DMA0
DMA10
VSS
VD33
DMA1
1
DRAS2#
DRAS1#
DCS1#
DCS0#
DRAS0#
VSS
VDD
DCAS#
DOE#
DWE#
DSCK
DQM
DB7
VSS
VD33
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VD33
DB8
DB9
DB10
DB1
1
DB12
DB13
VSS
SPDIF_IN
VD33PLL
AV
D
D
3
VREFIN
VREFOUT
RFENV
TE
CE
FE
BSUM
LDON
MIRR
DFCT
SCLK
SDA
T
A
SDEN
IP2
LG
LDCO
RX
VSS
TX
AUX3[0]/CAMIN0
AUX3[5]/CAMIN5
VDD
VSS
RXD1/AUX1[2]
TXD1/AUX1[3]
VD33
MCLK
RXD0/AUX1[4]/AOUT_O4R
TXD0/AUX1[5]/AOUT_O4L
TBCK/AOUT_O1R
TSD3/AOUT_O3R
TSD2/AOUT_O3L
VSS
VD33
TSD1/AOUT_O2R
TSD0/AOUT_O2L
TWS/AOUT_O1L
ADC_CAP
MIC
ADC_BIAS
UDAC/YUV0/PIXOUT0
CDAC/YUV2/PIXOUT2
YDAC/YUV5/PIXOUT5
VS33DAC
VD33DAC
VDAC/YUV6/PIXOUT6
FDAC/YUV7/PIXOUT7
RSET/YUV4/PIXOUT4
COMP/YUV3/PIXOUT3
VREF/YUV1/PIXOUT1
VS33PLL
SPDIF_OUT
LA1
LOE#
LD0
LD1
VD33
VSS
LD2
LD3
LD4
LD5
LD6
LD7
LCS3#
VDD
VSS
LCS2#
LCS1#
LCS0#
LA0
LA17
LA2
VD33
VSS
LA3
LA4
LA1
LOE#
LD0
LD1
VD33
VSS
LD2
LD3
LD4
LD5
LD6
LD7
LCS3#
VDD
VSS
LCS2#
LCS1#
LCS0#
LA0
LA17
LA2
VD33
VSS
LA3
LA4
LA6
LA7
VDD
VSS
LA8
LA18
LA19
LWRLL#
LA21
LA20
LA9
LA10
VD33
VSS
LA11
LA12
LA13
LA14
LA15
LA16
DB15
DB14
VD33
LA7
VDD
VSS
LA8
LA18
LA19
LWRLL#
LA21
LA20
LA9
LA10
VD33
VSS
LA11
LA12
LA13
LA14
LA15
LA16
DB15
DB14
VD33
LA5
ES6809
Figure 6: ES6809 DEVICE PINOUT
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