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HT-CN410DVH

49

IC201, Programmable Multimedia and DSP Processor (ES6809PADF)

VD33

1, 11, 20, 36, 45, 53, 63, 80, 97, 

122, 130, 156, 182, 197

P

I/O power supply.

AUX0

2

I/O

Host control 0.

AUX3

3

I/O

Auxiliary port 3.

RESET#

4

I

Reset (active-low).

AUX1

5

I/O

Host control 1.

DMA11:0

6:9, 12:18, 21

O

DRAM address bus.

VSS

10, 19, 27, 35, 44, 52, 62, 72, 79,

87, 96, 123,133, 138, 183,

196, 201, 208

G

Ground.

DRAS2-0#

22, 23, 26

O

DRAM row address strobes (active-low).

DCS1-0#

24, 25

O

DRAM chip selects (active-low).

VDD

28, 73, 88, 134, 202

P

Core power supply.

DCAS#

29

O

DRAM column address strobes (active-low).

DOE#

30

O

DRAM output enable (active-low).

DWE#

31

O

DRAM write enable (active-low).

DSCK

32

O

Output clock to DRAM.

DQM

33

O

Data input/output mask.

DB15-0

34, 37:43, 46:51, 54,55

I/O

DRAM data bus.

LA21-0

56:61, 64:67, 69:71,

74:78, 81:83, 101

O

SRAM address bus.

LWRLL#

68

O

SRAM bus write enable (active-low).

LCS3-0#

84:76, 89

O

SRAM bus chip select (active-low).

LD7-0

90:95, 98, 99

I/O

SRAM data bus.

LOE#

100

O

RISC port output enable (active-low).

SPDIF_OUT

102

O

S/PDIF output.

SPDIF_IN

103

I

S/PDIF input.

VD33PLL

104

P

Power for PLL blocks.

VS33PLL

105

G

Ground for PLL blocks.

VREF

106

I

Internal voltage reference to video DAC.

YUV1

O

YUV pixel 1 output data.

PIXOUT1

O

CCIR656 output pixel 1.

COMP

107

I

Compensation input.

YUV3

O

YUV pixel 3 ouput data.

PIXOUT3

O

CCIR656 output pixel 3.

RSET

108

I

DAC current adjustment resistor input.

YUV4

O

YUV pixel 4 output data.

PIXOUT4

O

CCIR656 output pixel 4.

FDAC

109

O

VideoDAC output. Refer to description and matrix for UDAC pin 115.

YUV7

O

YUV pixel 7 ouput data.

PIXOUT7

O

CCIR656 output pixel 7.

HT-CN410DVH

50

IC201, Programmable Multimedia and DSP Processor (ES6809PADF)

Table 1 ES6809 Pin Description (Continued):

VDAC

110

O

VideoDAC output. Refer to description and matrix for UDAC pin 115.

YUV6

O

YUV pixel 6 ouput data.

PIXOUT6

O

CCIR656 output pixel 6.

VD33_DA

111

P

Poer for I/O power supply for VDAC.

VS33_DA

112

G

Ground for I/O power supply for VDAC.

YDAC

113

O

VideoDAC output. Refer to description and matrix for UDAC pin 115.

YUV5

O

YUV pixel 5 ouput data.

PIXOUT5

O

CCIR656 output pixel 5.

CDAC

114

O

VideoDAC output. Refer to description and matrix for UDAC pin 115.

YUV2

O

YUV pixel 2 ouput data.

PIXOUT2

O

CCIR656 output pixel 2.

UDAC

115

O

Video DAC ouput

YUV0

O

YUV pixel 0 output data.

PIXOUT0

O

CCIR665 ouput pixel 0.

ADC_BIAS

116

O

Audio ADC bias voltage out.

MIC

117

I

Audio ADC MIC 1.

ADC_CAP

118

O

Audio ADC output capacitance.

TWS

119

O

Audio transmit frame sync output.

AOUT_O1L

O

Audio left channel 1 out.

TSD0

120

O

Audio transmit serial data port 0.

AOUT_O2L

O

Audio left channel 2 out.

TSD1

121

O

Audio transmit serial data port 1.

AOUT_O2R

O

Audio right channel 2 out.

F :  CVBS/Chroma signal for simultaneous mode.
Y : Luma component for YUV and Y/C processing.
C : Chrominance signal for Y/C processing.
U : Chrominance component signal for YUV mode.
V : Chrominance component signal for YUV mode.

0

CVBS/Chroma

CVBS1

Y

C N/A

1

CVBS/Chroma

CVBS1

Y

C CVBS2

2

CVBS/Chroma

  N/A

Y

C 

N/A

3

CVBS/Chroma

CVBS1

 N/A

 N/A

CVBS2

4

CVBS/Chroma

CVBS1

 N/A

 N/A

 N/A

5

CVBS/Chroma

CVBS1

Y

Pb

Pr

6

CVBS/Chroma

  N/A

Y

Pb

Pr

7

  N/A

SYNC

G

B

R

8

CVBS/Chroma

Chroma

Y

Pb

Pr

9

 CVBS

CVBS1

G

B

R

10

 CVBS

CVBS1

G

R

B

11

  N/A

SYNC

G

R

B

12

CVBS/Chroma

  N/A

Y

Pr

Pb

13

CVBS/Chroma

CVBS1

Y

Pr

Pb

14

    Chroma

Y

G

R

B

HT-CN410DVH

51

IC201, Programmable Multimedia and DSP Processor (ES6809PADF)

Table 1 ES6809 Pin Description (Continued):

TSD2

124

O

Audio transmit serial data port 2.

AOUT_O3L

O

Audio left channel 3 out.

TSD3

125

O

Audio transmit serial data port 3.

AOUT_O3R

O

Audio right channel 3 out.

TBCK

126

O

Audio transmit bit clock.

AOUT_O1R

O

Audio right channel 1 out.

TXD0

127

I/O

Serial port 0 transmit.

AOUT_O4L

I/O

Audio left channel 4 out.

RXD0

128

I/O

Serial port 0 receive.

AOUT_O4R

I/O

Audio right channel 4 out.

MCLK

129

I/O

Audio master clock for audio DAC.

TXD1

131

I/O

Serial port 1 transmit.

RXD1

132

I/O

Serial port 1 receive.

AUX3[5]

135

I/O

AUX3 data I/O 5.

CAMIN[5]

I/O

Camera I/O 5.

AUX3[0]

136

I/O

AUX3 data I/O 0.

CAMIN[0]

I/O

Camera I/O 0.

TX

137

I

Zero crossing of TE.

RX

139

I

Zero crossing of RF envelope.

LDCO

140

O

CD/DVD laser diode sekect.

LG

141

O

DVD-RAM land/groove flag for next track.

IP2

142

I

DVD-RAM header position index 2.

SDEN

143

O

RF chip serial data enable.

SDATA

144

I/O

Data signal to/from RF chip.

SCLK

145

O

Serial clock source to RF chip.

DFCT

146

I

Detect flag input signal.

MIRR

147

I

Mirror detect input.

LDON

148

O

Laser diode on/off control.

BSUM

149

I

Photodiode subbeam addition input signal.

FE

150

I

Focus input error signal.

CE

151

I

centre error input signal.

TE

152

I

Tracking error input.

RFENV

153

I

RF ripple envelope input signal.

VREFOUT

154

I

Reference voltage for servo analog output signals.

VREFIN

155

I

Reference voltage for servo analog input signals.

DMO

159

O

Spindle drive.

FOO

160

O

Focus drive.

SLO

161

O

Sled drive.

RPBC

162

O

RF envelope balance control.

TRO

163

O

Track drive.

NC

164

O

No connect.

TEBC

165

O

Tracking error balance control.

REFD

166

I

Flash reference decouple.

IN_M

167

I

Analog RF signal (minus).

IN

168

I

Analog RF signal (plus).

HT-CN410DVH

 52

IC201, Programmable Multimedia and DSP Processor (ES6809PADF)

Table 1 ES6809 Pin Description (Continued):

AVDD3

169

P

3.3V analog power for flash.

AVSS

170

G

Analog ground for flash.

DVCC

171

P

1.8V power for flash.

IP1

172

I

DVD-RAM header position index 1.

IDSEL

173

I/O

DVD-RAM detected signal of ID area.

AMPSTBY

174

O

Power amplifier standby.

FGIN

175

I

Spindle hall sensor input.

CLOSESW

176

I

Tray closed detector.

HOMESW

177

I

Sled home switch position detector.

CLOSE

178

O

Drive to open tray.

OPENSW

179

I

Tray open detector.

OPEN

180

O

Drive to open tray.

MDET

181

I

Spindle drive motor rotation direction detect.

AUX7

184

I/O

Auxiliary port 7.

AUX3[7]

185

I/O

Aux3 data I/O 7.

CAMIN7

I/O

Camera I/O 7.

EAUX1

186

I/O

Extended auxiliary port 1.

AUX3[6]

187

I/O

Aux3 data I/O 6.

CAMIN6

I/O

Camera I/O 6.

EAUX0

188

I/O

Extended auxiliary port 0.

CAM_CLK

I/O

Camera clock.

EAUX3

189

I/O

Extended auxiliary port 3.

PCLKQSCN

O

13.5-MHz video output pixel clock.

AUX4[1]

I/O

Aux4 data I/O; (5V tolerant input).

EAUX2

190

I/O

Extended auxiliary port 2.

PCLK2XSCN

I/O

27-MHz video output pixel clock.

AUX4[0]

I/O

Aux4 data I/O 0.

VSYNC#

191

I/O

Vertical sync (active-low); (5V tolerant input).

AUX1[7]

I/O

Aux1 data I/O 7.

HSYNC#

192

I/O

Horizontal sync (active-low): (5V tolerant input).

AUX1[6]

I/O

Aux1 data I/O 6.

XI

193

I

Crystal clock in.

XO

194

O

Crystal clock out.

AUX3[4]

198

I/O

Aux3 data I/O 4.

CAMIN4

I/O

Camera I/O 4.

AUX3[1]

199

I/O

Aux3 data I/O 1.

CAMIN1

I/O

Camera I/O 1.

AUX3[3]

200

I/O

Aux3 data I/O 3.

CAMIN3

I/O

Camera I/O 3.

AUX3[2]

203

I/O

Aux3 data I/O 2.

CAMIN2

I/O

Camera I/O 2.

AUX6-4, 2

204-207

I/O

Auxiliary ports 2,4,5 and 6; (5V tolerant input).