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HT-CN410DVH

53

IC203, EEPROM (AT24C02N-10SU-2.7)

IC801, DVD Servo (ES6602SF)

ES6602 PINOUT

Figure 7: ES6602 DEVICE PINOUT

8-lead SOIC

1

2

3

4

8

7

6

5

A0

A1

A2

GND

VCC

WP

SCL

SDA

A0 - A2

Address Inputs

SDA

Serial Data

SCL

Serial Clock Input

WP

Write Protect

NC

No Connect

GND

Ground

VCC

Power Supply

Table 1 EEPROM Pin Configuration

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

PIO

MIN

MLPF

MB

MP

MIRR

LDON

VNB

CDPD

DVDPD

CDLD

DVDLD

VC

VPB

CD_E

CD_F

DVDRFP

DVDRFN

A2

B2

C2

D2

CP

CN

D

C

B

A

NC

NC

NC

NC

SDEN

SDATA

SCLK

V33

NC

NC

MNTR

NC

FE

TE

PI

NC

V165

DB

DFT

MMON

RX

NC

VNA

FNN

FNP

DIP

DIN

BYP

RFAC

VPA

AIP

AIN

ATON

ATOP

RFSIN

NC

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

48

47

46 45 44 43 42 41

40 39

38 37 36 35 34

33

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15

16

ES6602

HT-CN410DVH

54

IC801, DVD Servo (ES6602SF)

ES6602 PIN DESCRIPTION

DVDRFP, DVDRFN

1,2

I

Differential RF signal attenuator inputs.

A2, B2, C2, D2

3-6

I

AC coupled photo detector interface input for the differential phase 
detector (DPD) from the main beam photo matrix.

CP, CN

7, 8

_

Differential phase tracking low-pass filter pins. Connect CP to CN via 
capacitors.

D, C, B, A

9-12.

I

Photo detector interface input from the main beam photo matrix.

NC

13-16, 37, 41, 43, 44, 50, 64

I

No connect

CD_F, CD_E

17, 18

I

CD photo detector interface input from the CD side beam photo 
detector; used for CD tracking detection.

VPB

19

P

Servo block power supply.

VC

20

O

Reference voltage out (VPB/2). Output impedance is less than 50

Ω

DVDLD

21

O

DVD APC output; controls laser power for DVD.

CDLD

22

O

CD APC output; controls laser power for CD.

DVDPD

23

I

DVD APC input

CDPD

24

I

CD APC input

VNB

25

G

Servo block ground

LDON

26

I

APC On/Off control. A high level activates LD Output. (open is low)

MIRR

27

O

Mirror detect output

MP, MB

28, 29

I

Mirror top and bottom hold pins. Connected to VPB pin 19 via 
capacitors.

MLPF

30

I

Mirror low-pass filter pin. Connected to VPB pin 19 via a capacitor.

MIN

31

I

RF input signal for mirror. AC coupled input for the mirror detection 
circuit from MEVO pin 32.

PIO

32

O

Buffered Pull-In Signal Output; This is the PI (pin 38) with gain (18 or 
24dB - see CCR register 2Ch, bit 6).

MMON

33

O

Mirror Monitor Output: When the monitor output signal is selected by 
bits 3:0 of the CER register 3Ch, mirror-related signals can be 
observed.

DFT

34

O

Defect Output: When the Pull-In signal level is below the detection 
level, or when the RF signal level is below the detection level, the 
DFT output goes high. The defect output is selected by the serial port.

DB

35

I

Defect Bottom Hold: Connected to VPB pin 19 via a capacitor.

V165

36

O

1.65V servo block reference voltage output.

PI

38

O

Pull-In Signal Out: The summing signal output of A, B, C, D, or CD_A, 
CD_B, CD_C, or CD_D. Reference to V25/3.

TE

39

O

Tracking error output reference to V125 pin 36.

FE

40

O

Focusing error output reference to V125 pin 36.

MNTR

42

O

Monitor out signal. Output is selectable by register settings.

V33

45

P

3.3V output buffers power supply.

SCLK

46

I

Serial clock from Vibratto-II.

SDATA

47

I/O

Serial data I/O.

SDEN

48

I

Serial date enable. Enabled By an active-high signal.

RX

49

I

Reference resistor. Connected to ground via a 12,0k

Ω, 1% resistor.

HT-CN410DVH

55

IC303, 192 kHz Multi-bit audio A/D Converter (CS5342)

Figure 8: FUNCTIONAL BLOCK DIAGRAM

IC303, 192 kHz Multi-bit audio A/D Converter (CS5342)

Pin Description:

Table 1 ES6602 Pin Description List (Continued)

VNA

51

G

RF block and serial port ground.

FNN, FNP

52, 53

O

Differential outputs of equalizer/filter.

DIP, DIN

54, 55

I

Differential analog input to the RF single-end output buffer and full 
wave rectifier.

BYP

56

I

AGC amplifier gain bypass. Tied to VPA via a capacitor.

RFAC

57

O

Single-ended RF output.

VPA

58

P

RF block and serial port power supply.

AIP, AIN

59, 60

I

Differential AGC amplifier inputs.

ATON ATOP

61, 62

O

Differential attenuator outputs.

RFSIN

63

I

Single-ended RF signal attenuator input.

VQ

REFGND

GND

AINR

AINL

FILT+

SCLK LRCK SDOUT

MCLK

V

L

2.5V - 5.0V

VD

3.3V - 5.0V

VA

3.3V - 5.0V

RST

M0

M1

Serial Output Interface

Voltage Reference

LP Filter

LP Filter

DAC

Q

Q

DAC

S/H

S/H

+

-

+

-

Digital

Decimation

Filter

High

Pass
Filter

High

Pass
Filter

Digital

Decimation

Filter

M0

MCLK

VL

SDOUT

GND

VD

SCLK

LRCK

M1

FILT+

REFGND

VA

AINR

VQ

AINL

RST

1

16

15

14

13

12

11

10

9

2

3

4

5

6

7

8

HT-CN410DVH

56

IC303, 192 kHz Multi-bit audio A/D Converter (CS5342)

IC5002, Headphone Driver with Mute (APA 3541-TRL)

Block Diagram

M0

1

Mode Selection (Input) - Determines the operational mode of the device.

M1

16

MCLK

2

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

VL

3

Logic Power (Input) - Positive power for the digital input/output.

SDOUT

4

Serial Audio Data Output (Output) - Output for two's complement serial audio data.

GND

5

Ground (Input) - Ground reference. Must be connected to analog ground.

VD

6

Digital Power (Input) - Positive power supply for the digital section.

SCLK

7

Serial Clock (Input/Output) - Serial clock for the serial audio interface.

LRCK

8

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio data line.

RST

9

Reset (Input) - The device enters a low power mode when low.

AINL

10

Analog Input (Input) - The Full scale analog input level is specified in the Analog

AINR

12

Characteristics specification table.

VQ

11

Quiescent Voltage (Output) - Filter connection for the internal quiescent
reference voltage.

VA

13

Analog Power (Input) - Positive power supply for the analog section.

REFGND

14

Reference Ground (Output) - Ground reference for the internal sampling circuits.

FILT+

15

Positive Voltage Reference (Output) - Positive reference voltage for the internal
sampling circuits.

Input B

O u t B

B I A S

M u t e

O u t A

Input A

B IA S

+

A

B

+

1

2

3

4

V

S S

5

6

7

8

V

D D

0 d B

(6 d B)

0 d B

(6 d B )

1 8 0 k

Ω

( 9 0 k

Ω)

1 8 0 k

Ω

( 9 0 k

Ω)

* The values in parenthessis are for the APA3544.

M U T E