Sharp HT-CN410DVH (serv.man2) Service Manual ▷ View online
HT-CN410DVH
57
IC5002, Headphone Driver with Mute (APA 3541-TRL)
Function Pin Description
IC501, Multi Channel Digital Audio (STA308A)
Figure 9: BLOCK DIAGRAM
Pin Name
I/O
Function Description
Out A
O
A channel output pin
Mute
I
Chip disable control input, low active and high for normal operating
Input A
I
A channel input terminal
V
SS
Power ground pin
Input B
I
B channel input terminal
BIAS
I
Right channel bias input pin
OUT B
O
B channel output pin
V
DD
Power input pin
OUT1A/B
OUT2A/B
OUT3A/B
OUT4A/B
OUT5A/B
OUT6A/B
OUT7A/B
OUT8A/B
LRCKO
BICKO
SDO12
SDO12
SDO34
SDO56
SDO56
SDO78
DDX
OVERSAMPLING
VOLUME
LIMITING
POWER
DOWN
SYSTEM TIMING
PLLB
XTI
CKOUT
SDI78
SDI56
SDI34
SDI12
BICKI
LRCKI
SA
SCL SDA
MVO
PWDN
EAPD
PLL
SERIAL
DATE
IN
SYSTEM
CONTROL
I
2
C
CHANNEL
MAPPING
TREBLE
BASS, EQ
(BIQUADS)
VARIABLE
OVER-
SAMPLING
VARIABLE
DOWN-
SAMPLING
SERIAL
DATA
OUT
HT-CN410DVH
58
IC501, Multi Channel Digital Audio (STA308A)
Pin Connection (Top view)
Table 1. Pin Function
Pin
Name
Description
Pad Type
1
MVO/DSD_CLK
Master Volume Override/
DSD Input Clock
DSD Input Clock
5V Tolerant TTL Input Buffer
6
SDI_78/DSD_6
Input Serial Data Channels 7 & 8/
DSD Input Channel 6
DSD Input Channel 6
5V Tolerant TTL Input Buffer
7
SDI_56/DSD_5
Input Serial Data Channels 5 & 6/
DSD Input Channel 5
DSD Input Channel 5
5V Tolerant TTL Input Buffer
8
SDI_34/DSD_4
Input Serial Data Channels 3 & 4/
DSD Input Channel 4
DSD Input Channel 4
5V Tolerant TTL Input Buffer
9
SDI_12/DSD_3
Input Serial Data Channels 1 & 2/
DSD Input Channel 3
DSD Input Channel 3
5V Tolerant TTL Input Buffer
10
LRCKI/DSD_2
Input Left/Right Clock/
DSD Input Channel 2
DSD Input Channel 2
5V Tolerant TTL Input Buffer
11
BICKI/DSD_1
Input Serial Clock/
DSD Input Channel 1
DSD Input Channel 1
5V Tolerant TTL Input Buffer
15
RESET
Global Reset
5V Tolerant TTL Schmitt Trigger Input Buffer.
16
PLL_BYPASS
Bypass Phase Locked Loop
CMOS Input Buffer with Pull-Down
17
SA
Select Address (I
2
C)
CMOS Input Buffer with Pull-Down
18
SDA
I
2
C Serial Data
Bidirectional Buffer: 5V Tolerant TTL Schmitt
Trigger Input; 3.3V Capable 2mA Slew-rate
controlled Output.
Trigger Input; 3.3V Capable 2mA Slew-rate
controlled Output.
19
SCL
I
2
C Serial Clock
5V Tolerant TTLSchmitt Trigger Input Buffer
20
XTI
Crystal Oscillator Input (Clock Input)
5V Tolerant TTLSchmitt Trigger Input Buffer
21
FILTER_PLL
PLLFilter
Analog Pad
22
VDDA
PLL Supply
3.3V Analog Power Supply Voltage
23
GNDA
PLL Ground
Analog Ground
25
CKOUT
Clock Output
3.3V Capable TTL Tristate 4mA Output Buffer
29
OUT8B
PWM Channel 8 Output B
3.3V Capable TTL 2mA Output Buffer
OUT2_A
OUT2_B
NC
GND
VDD
OUT3_A
OUT3_B
OUT4_A
OUT2_B
NC
GND
VDD
OUT3_A
OUT3_B
OUT4_A
OUT4_B
OUT5_A
OUT5_B
NC
GND
VDD
OUT6_A
OUT6_B
OUT5_A
OUT5_B
NC
GND
VDD
OUT6_A
OUT6_B
48
47
46
45
44
43
42
41
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
39
38
37
36
35
34
33
PWDN
SDO
78
SDO
56
NC
GND
VDD
SDO_34
SDO_12
LRCKO
BICKO
NC
GND
VDD
EAPD
OUT1_A
OUT1_B
MVO
GND
VDD
GND
NC
SDI_78
SDI_56
SDI_34
SDI_56
SDI_34
SDI_12
LRCKI
BICKI
VDD
GND
NC
RESET
PLLB
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
SA
SDA
SCL
XTI
FILTER
PLL
VDDA
GNDA
VDD
CKOUT
NC
GND
VDD
OUT8_B
OUT8_A
OUT7_B
OUT7_A
STA308APINCON
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
HT-CN410DVH
59
IC501, Multi Channel Digital Audio (STA308A)
Table 1. Pin Function (Continued)
Pin
Name
Description
Pad Type
30
OUT8A
PWM Channel 8 Output A
3.3V Capable TTL 2mA Output Buffer
31
OUT7B
PWM Channel 7 Output B
3.3V Capable TTL 2mA Output Buffer
32
OUT7A
PWM Channel 7 Output A
3.3V Capable TTL 2mA Output Buffer
33
OUT6B
PWM Channel 6 Output B
3.3V Capable TTL 2mA Output Buffer
34
OUT6A
PWM Channel 6 Output A
3.3V Capable TTL 2mA Output Buffer
38
OUT5B
PWM Channel 5 Output B
3.3V Capable TTL 2mA Output Buffer
39
OUT5A
PWM Channel 5 Output A
3.3V Capable TTL 2mA Output Buffer
40
OUT4B
PWM Channel 4 Output B
3.3V Capable TTL 2mA Output Buffer
41
OUT4A
PWM Channel 4 Output A
3.3V Capable TTL 2mA Output Buffer
42
OUT3B
PWM Channel 3 Output B
3.3V Capable TTL 2mA Output Buffer
43
OUT3A
PWM Channel 3 Output A
3.3V Capable TTL 2mA Output Buffer
47
OUT2B
PWM Channel 2 Output B
3.3V Capable TTL 2mA Output Buffer
48
OUT2A
PWM Channel 2 Output A
3.3V Capable TTL 2mA Output Buffer
49
OUT1B
PWM Channel 1 Output B
3.3V Capable TTL 2mA Output Buffer
50
OUT1A
PWM Channel 1 Output A
3.3V Capable TTL 2mA Output Buffer
51
EAPD
Ext.Amp Power Down
3.3V Capable TTL 2mA Output Buffer
55
BICKO
Output Serial Clock
3.3V Capable TTL 2mA Output Buffer
56
LRCKO
Output Left/Right Clock
3.3V Capable TTL 2mA Output Buffer
57
SDO_12
Output Serial Data Channels 1&2
3.3V Capable TTL 2mA Output Buffer
58
SDO_34
Output Serial Data Channels 3&4
3.3V Capable TTL 2mA Output Buffer
3, 12, 24, 28,
35, 44, 52, 59
VDD
3.3V Supply
3.3V Digital Power Supply Voltage
2, 4, 13, 27,
36, 45, 53, 60
GND
Ground
Digital Ground
5, 14, 26, 37,
46, 54, 61
NC
No Connect
62
SDO_56
Output Serial Data Channels 5&6
3.3V Capable TTL 2mA Output Buffer
63
SDO_78
Output Serial Data Channels 7&8
3.3V Capable TTL 2mA Output Buffer
64
PWDN
Device Power Down
5V Tolerant TTL Schmitt Trigger Input Buffer
HT-CN410DVH
60
IC502 & IC504, Power Half Bridge (STA518)
Table 1. Pin Function
No
Pin
Description
1
GND-SUB
Substrate ground
35 ; 36
Vcc Sign
Signal Positive supply
15
Vcc1A
Positive supply
12
Vcc1B
Positive supply
7
Vcc2A
Positive supply
4
Vcc2B
Positive supply
14
GND1A
Negative Supply
13
GND1B
Negative Supply
6
GND2A
Negative Supply
5
GND2B
Negative Supply
16 ; 17
OUT1A
Output half bridge 1A
10 ; 11
OUT1B
Output half bridge 1B
8 ; 9
OUT2A
Output half bridge 2A
2 ; 3
OUT2B
Output half bridge 2B
29
IN1A
Input of half bridge 1A
30
IN1B
Input of half bridge 1B
31
IN2A
Input of half bridge 2A
32
IN2B
Input of half bridge 2B
21 ; 22
Vdd
5V Regulator referred to ground
33 ; 34
Vss
5V Regulator referred to + Vcc
25
PWRDN
Stand-by pin
26
TRI-STATE
Hi-Z pin
27
FAULT
Fault pin advisor
24
CONFIG
Configuration pin
28
TH-WAR
Thermal warning advisor
19
GND-clean
Logical ground
23
VL
Logic Reference Voltage
18
NC
Not connected
20
GND-Reg
Ground for regulator Vdd
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