Panasonic KX-TGP600RUB / KX-TPA60RUB Service Manual ▷ View online
89
KX-TGP600RUB/KX-TPA60RUB
17.1.3.
IC102 (Flash)
Pin No.
Terminal Name
I/O setting
Contens of Control
Pull-up/down
Processing
Remark
1
NC
-
-
-
-
2
NC
-
-
-
-
3
NC
-
-
-
-
4
NC
-
-
-
-
5
NC
-
-
-
-
6
NC
-
-
-
-
7
R/*B
O
NFLREADY
Pull Up via R133
READY / BUSY
8
*RE
I
NFLRD
READ ENABLE
9
*CE
I
NFLCS0
CHIP SELECT
10
NC
-
-
-
-
11
NC
-
-
-
-
12
VCC
P
3.2V
13
VSS
G
DG
14
NC
-
-
-
-
15
NC
-
-
-
-
16
CLE
I
NFLCLE
COMMAND LATCH ENABLE
17
ALE
I
NFLALE
ADDRESS LATCH ENABLE
18
*WE
I
NFLWR
WRITE ENABLE
19
*WP
I
Pull Up via R134
write protect
20
NC
-
-
-
-
21
NC
-
-
-
-
22
NC
-
-
-
-
23
NC
-
-
-
-
24
NC
-
-
-
-
25
NC
-
-
-
-
26
NC
-
-
-
-
27
NC
-
-
-
-
28
NC
-
-
-
-
29
I/O0
I/O
NFLD0
DATA
30
I/O1
I/O
NFLD1
DATA
31
I/O2
I/O
NFLD2
DATA
32
I/O3
I/O
NFLD3
DATA
33
NC
-
-
-
-
34
NC
-
-
-
-
35
NC
-
-
-
-
36
VSS
G
DG
37
VCC
P
3.2V
VCC
38
NC
-
-
-
-
39
NC
-
-
-
-
40
NC
-
-
-
-
41
I/O4
I/O
NFLD4
DATA
42
I/O5
I/O
NFLD5
DATA
43
I/O6
I/O
NFLD6
DATA
44
I/O7
I/O
NFLD7
DATA
45
NC
-
-
-
-
46
NC
-
-
-
-
47
NC
-
-
-
-
48
NC
-
-
-
-
90
KX-TGP600RUB/KX-TPA60RUB
17.1.4.
IC300 (DCX)
Pin No.
Terminal Name
I/O setting
Contens of Control
Pull-up/down
Processing
Remark
1
DQ1
I/O
DQ1_1
2
QSCLK
O
C_1
3
DQ3
I/O
DQ3_1
Pull Up via R313
4
DQ2
I/O
DQ2_1
5
DQ0
I / O
DQ0_1
6
VDD_DPU_DAIF
I
1.8V
VDD
7
VDD
I
1.2V
VDD
8
COREOUT
O
Internal DPU core
power output (1.2V)
power output (1.2V)
VDD 1.2V out put
9
VBAT
P
3.2V
VDD
10
DOUBCAP2N
-
-
-
-
11
DOUBCAP2P
-
-
-
-
12
DOUBCAP1N
-
-
-
-
13
DOUBCAP1P
-
-
-
-
14
DOUT3V0
-
-
-
-
15
DOUT4V5
-
-
-
-
16
DOUT2V5
-
-
-
-
DCIN0
-
-
LIN0
-
-
17
LEDSINK2
-
-
-
-
DCIN1
-
-
-
-
18
DCIN2
-
-
-
-
19
DCIN3
-
-
-
-
LIN1
-
-
-
-
20
LEDSINK1
I/O
-
-
-
PWM1
-
-
21
VREF
O
VREF
22
VCCA
P
3.2V
VCC
23
MIN
-
-
-
-
24
MIP
-
-
-
-
25
HSMIN
-
-
-
-
26
HSMIP
-
-
-
-
27
MPWR
-
-
-
-
28
SPOUTP
-
-
-
-
29
VCCPA
P
3.2V
VCC
30
SPOUTN
-
-
-
-
31
HSSPOUTP
-
-
-
-
32
LOUT
-
-
-
-
33
PWM0
-
-
-
-
34
DCINS
-
-
-
-
35
XOUT
-
-
-
-
36
XIN
I
BCLK
CLOCK IN
37
VDD_APU
O
1.8Voutput
VDD OUT
38
VBAT_APU
P
3.1V
VDD
39
VDD_IF
O
1.8V
VDD OUT
40
VCC_FE_IF
P
3.1V
VCC
41
VCC_PA
P
3.1V
VCC
42
BAL_OUT2
O
BAL_OUT2
RF
43
BAL_OUT1
I
BAL_OUT1
RF
44
TX_SW
O
TX-SW
RF
45
ANT1
I/O
ANT1
RF
46
GND_RF
-
DG
47
ANT2
I/O
ANT2
RF
48
TEST
-
-
-
-
49
RX_SW
I
RX-SW
RF
50
LNA_INN
I
LNA_INN
RF
51
LNA_INP
I
LNA_INP
RF
52
ATST_P
-
-
-
-
EXT_LNA
-
-
-
-
53
RSTN
I
DCX1_RST
RESET
54
VCC_VCO
I
VCC_VCO
55
GPIO17
-
-
-
-
ON/OFF
-
-
91
KX-TGP600RUB/KX-TPA60RUB
56
VDD
I
1.2V
VCC
57
GPIO0
-
-
-
-
58
GPIO1
-
-
-
-
59
GPIO2
O
TDMA_RXD
for TDM
60
GPIO3
I
TDMA_TXD
for TDM
61
GPIO4
I
TDMA_FSYNC
for TDM
62
VCC
I
3.1V
VCC
63
GPIO5
I/O
TDMA_SCLK
for TDM
64
GPIO6
-
-
-
-
65
GPIO7
-
-
-
-
66
GPIO8
-
-
-
-
67
GPIO9
-
-
-
-
68
TDO
O
TDO_1
69
TDI
I
TDI_1
Pull Up via R310
70
TCK
I
TCK_1
71
TMS
I
TMS_1
72
RTCK
O
RTCK_1
73
GPIO10
-
-
-
-
74
VDD
P
1.2V
VDD
75
VCC
P
3.1V
VCC
76
GPIO11
I
SPI1_DO
77
GPIO12
O
SPI1_DI
78
GPIO13
I
SPI1_CLK
79
GPIO14
I
SPI1_CS0
80
GPIO15
I
URX
Pull Up via R315
URX
81
GPIO16
O
UTX
UTX
82
GPIO18
I
DCX1_BOOT
83
GPIO19
O
DVF_READY
84
GPIO20
I
DVF_TXREQ
85
GPIO21
O
DCX1_TXREQ
86
GPIO22
I
DCX1_READY
87
QCSN0
O
S#_1
88
QVCC
I
3.2V
VCC
Pin No.
Terminal Name
I/O setting
Contens of Control
Pull-up/down
Processing
Remark
92
KX-TGP600RUB/KX-TPA60RUB
17.1.5.
IC301 (Flash)
17.1.6.
IC200 (PHY)
Pin No.
Terminal Name
I/O setting
Contens of Control
Pull-up/down
Processing
Remark
1
*CS
I
S#_1
chip select
2
DO/IO1
I/O
DQ1_1
-
3
*WP/IO2
I/O
DQ2_1
-
4
GND
G
DG
-
5
DI/IO0
I/O
DQ0_1
-
6
CLK
I
C_1
CLOCK
7
*HOLD/IO3
I/O
DQ3_1
Puu Up Via R313
-
8
VCC
P
VCC
VCC 1.8V
Pin No.
Terminal Name
I/O setting
Contens of Control
Pull-up/down Processing
Remark
1
RSET
I
PSET
Pull Down via R240
Transmit Bias resistor
2
AVDD10OUT
O
-
Power Out Put
3
MDI+0
I/O
MDI+0
ETHER IF
4
MDI-0
I/O
MDI-0
ETHER IF
5
MDI+1
I/O
MDI+1
ETHER IF
6
MDI-1
I/O
MDI-1
ETHER IF
7
AVDD33_1
P
3.2V
Bias
8
RXDV
O
MII_RXDV
Recive Data Valid.
9
RXD0
O
MII_RXD0
Recive data
10
RXD1
O
MII_RXD1
Recive data
11
RXD2/INTB
O
MII_RXD2
Recive data
12
RXD3/CLK_CTL
O
MII_RXD3
Recive data
13
RXC
O
MII_RXCK
CLOCK for Recive data
14
DVDD33
P
3.2V
Bias
15
TXC
O
MII_TXC
CLOCK for Trancmit data
16
TXD0
I
MII_TXD0
Transmit Data
17
TXD1
I
MII_TXD0
Transmit Data
18
TXD2
I
MII_TXD0
Transmit Data
19
TXD3
I
MII_TXD0
Transmit Data
20
TXEN
I
MII_TXEN
Transmit Enable
21
PHYRSTB
I
PHY_RST
Reset
22
MDC
I
MDC
Pull Up via R238 and R239
Management Data Clock
23
MDIO
I/O
MDIO
Management Data Input/Output
24
NC
-
-
-
-
25
NC
-
-
-
-
26
CRS/CRS_DV
O
MII_CRS
Carrier Valid at harf duplex
27
COL
O
MII_COL
Collision detect
28
RXER/FXEN
O
MII_RXER
Pull down via R233
Recive Error
29
DVDD10OUT
O
-
Powe Out
30
AVDD33_2
P
3.2V
Bias
31
CKXTAL1
I
X200
crystal osc.
32
CKXTAL2
O
X200
crystal osc.
33
GND
G
DG
-
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