Panasonic KX-TGP600RUB / KX-TPA60RUB Service Manual ▷ View online
85
KX-TGP600RUB/KX-TPA60RUB
P 7
KEY_COL6
O
TRACECLK
P 8
KEY_ROW9
I/O
TRACEDAT 5
P 9
KEY_ROW8
I/O
TRACEDAT 6
P10
KEY_ROW7_IIC2SDA
I/O
TRACEDAT 8
P11
U1CTS_DIGMIC_DATA
-
-
-
-
P12
DGPIO31
-
-
-
-
P13
TPX2
-
-
-
-
P14
VREF
O
VREF
P15
MICPWR0
-
-
-
-
P16
SINGIN1
-
-
-
-
P17
DCIN2
-
-
-
-
P18
TPS
-
-
-
-
P19
XO13M
O(A)
XO13M
crystal osc (13.824MHz)
R 1
MIIRXCK_RGMIIRXC
I
MII_RXCK
PHY CLOCK for Recive data
R 2
MIICRS_DV_RGMIIRX_CTL
I
MII_RXDV
PHY Recive Data Valid.
R 3
MIIRXD0_RGMIIRD0
I
MII_RXD0
PHY Recive Data
R 4
MDIO
I/O
MDIO
PHY Management Data Input/Output
R 5
NFLREADY1_MEMXA22
I
NFLREADY
Pull Up via R133
R 6
NFLD7_MEMXA21
I/O
NFLD7
R 7
EXTINT3_CLK_REF_OUT
I/O
EXTINT3/
CLK_REF_OUT
CLK_REF_OUT
Pull Up via R227
R 8
EXTINT1_IIC1SCL
-
-
-
-
R 9
KEY_ROW3
I/O
TRACEDAT14
R10
KEY_COL5
I
TRACECTL
R11
U1RX
I
VDF-URX1
Pull Up via R200
URX
R12
U1RTS_DIGMIC_CLK
-
-
-
-
R13
FORCEMUTE
I
FORCEMUTE
Pull Down via R145
R14
LEDSINK2
I
LEDSINK2
PWM LED CONTROL
R15
VDD12_DCLS
-
-
-
-
R16
VSS
G
GND
R17
VSS
G
GND
R18
TPY1
-
-
-
-
R19
DCIN0
-
-
-
-
T 1
MIITXEN_RGMIITX_CTL
O
MII_TXEN
PHY Transmit Enable
T 2
MIIREFCK_RGMIITXC
I
MII_TXCK
PHY CLOCK for Trancmit data
T 3
MIICOL_U2RX
I
MII_COL
PHY Collision detect
T 4
NFLRD_MEMXA24
O
NFLRD
T 5
NFLCS0_MEMXA18
O
NFLCS0
T 6
NFLD4_QDQ3
I/O
NFLD4
T 7
NFLD5_QCS0
I/O
NFLD5
T 8
KEY_ROW0
I/O
TRACEDAT 4
T 9
KEY_COL1
I/O
TRACEDAT 1
T10
KEY_COL4
I/O
TRACEDAT11
T11
U1TX
O
VDF-UTX1
Pull Down via R201
UTX
T12
TEST_ANA
I
DG
T13
EXT_REG_CTL
-
-
-
-
T14
DCDC_VSENS
-
-
-
-
T15
SINK_DCLS
G
GND
T16
SINK_DCLS
G
GND
T17
TPX1
-
-
-
-
T18
TPY2
-
-
-
-
T19
GNDI
G
GND
U 1
MIITXD1_RGMIITD1
O
MII_TXD1
PHY Transmit Data
U 2
MIITXD0_RGMIITD0
O
MII_TXD0
PHY Transmit Data
U 3
USB1N
I/O
USB1N
USB1 Negative
U 4
NFLALE_MEMXA17
O
NFLALE
U 5
NFLWR_MEMXA23
O
NFLWR
U 6
NFLD1_QDQ0
I/O
NFLD1
U 7
EXTINT0_IIC1SDA
-
-
-
-
U 8
KEY_ROW1
I/O
TRACEDAT15
U 9
KEY_COL0
I/O
TRACEDAT13
U10
KEY_ROW6_IIC2SCL
I/O
TRACEDAT 9
U11
EXTINT8_DRV_Vbus
-
-
-
-
U12
DCIN5
-
-
-
-
U13
PWM0
-
-
-
-
U14
VCC5V_DCDC
P
3.2V
-
Pin
No.
No.
Terminal Name
I/O setting
Contens of
Control
Pull-up/down Processing
Remark
86
KX-TGP600RUB/KX-TPA60RUB
U15
VDD18_DCLS
G
DG
U16
VCC5V_DCLS
P
3.2V
U17
VCC5V_DCLS
P
3.2V
U18
VSS
G
GND
U19
DCIN1
-
-
-
-
V 1
MIITXD3_RGMIITD3
O
MII_TXD3
PHY Transmit Data
V 2
MIITXD2_RGMIITD2
O
MII_TXD2
PHY Transmit Data
V 3
USB1P
I/O
USB1P
USB1 Positive
V 4
NFLD3_QDQ2
I/O
NFLD3
V 5
NFLCLE_MEMXA25
O
NFLCLE
V 6
NFLD2_QDQ1
I/O
NFLD2
V 7
EXTINT2_CLK_OUT
-
-
-
-
V 8
KEY_ROW4
I/O
TRACEDAT 2
V 9
KEY_COL3
I/O
TRACEDAT 0
V10
KEY_ROW5
I/O
TRACEDAT10
V11
SD_D0
-
-
-
-
V12
RSTN
I
RSTN
RESET
V13
LEDSINK1_PWM1
I
LEDSINK1
PWM LED CONTROL
V14
COIL_DCDC
-
-
-
-
V15
VDD18_DCDC
O
1.8V_APU
V16
VCC33SW_DCLS
P
3.2V
V17
VCC_ANA
P
3.2V
V18
PAOUTN
-
-
-
-
V19
PAOUTP
-
-
-
-
W 1
USB2N
-
-
-
-
W 2
USB2P
-
-
-
-
W 3
XI12M
I
XI12M
W 4
XO12M
O
XO12M
W 5
NFLD0_QCLK
I/O
NFLD0
W 6
NFLD6_QCS1
I/O
NFLD6
W 7
KEY_COL7_SPI2CS
-
-
-
-
W 8
KEY_ROW2
-
-
-
-
W 9
KEY_COL2
I/O
TRACEDAT12
W10
SD_CLK
-
-
-
-
W11
SD_CMD
-
-
-
-
W12
VCC_ANA
P
3.2V
W13
GND_DCDC
G
GND
W14
SINK_DCDC
P
GND
W15
DCDC_VRP
I
DCDC_VRP
W16
VCC33_DCDC
P
3.2V
W17
VDDSW_DCLS
G
DG
W18
VSS
G
GND
W19
DCIN3
-
-
-
-
Pin
No.
No.
Terminal Name
I/O setting
Contens of
Control
Pull-up/down Processing
Remark
87
KX-TGP600RUB/KX-TPA60RUB
17.1.2.
IC100 (DDR3)
Pin No.
Terminal Name
I/O setting
Contens of Control
Pull-up/down
Processing
Remark
A 1
VDDQ
P
1.5V
A 2
DQU5
I/O
DDR_DQ13
Data Inputs/Output:
A 3
DQU7
I/O
DDR_DQ15
Data Inputs/Output:
A 7
DQU4
I/O
DDR_DQU12
Data Inputs/Output:
A 8
VDDQ
P
1.5V
A 9
VSS
G
DG
B 1
VSSQ
G
DG
B 2
VDD
P
1.5V
B 3
VSS
G
DG
B 7
/DQSU
I/O
DDR_*UDQS
Data Strobe:
B 8
DQU6
I/O
DDR_DQ14
Data Inputs/Output:
B 9
VSSQ
G
DG
C 1
VDDQ
P
1.5V
C 2
DQU3
I/O
DDR_DQ11
Data Inputs/Output:
C 3
DQU1
I/O
DDR_DQ9
Data Inputs/Output:
C 7
DQSU
I/O
DDR_UDQS
Data Strobe:
C 8
DQU2
I/O
DDR_DQ10
Data Inputs/Output:
C 9
VDDQ
P
1.5V
D 1
VSSQ
G
DG
D 2
VDDQ
P
1.5V
D 3
DMU
I
DDR_UDM
Input Data Mask:
D 7
DQU0
I/O
DDR_DQ8
Data Inputs/Output:
D 8
VSSQ
G
DG
D 9
VDD
P
1.5V
E 1
VSS
G
DG
E 2
VSSQ
G
DG
E 3
DQL0
I/O
DDR_DQ0
Data Inputs/Output:
E 7
DML
I
DDR_LDM
Input Data Mask:
E 8
VSSQ
G
DG
E 9
VDDQ
P
1.5V
F 1
VDDQ
P
1.5V
F 2
DQL2
I/O
DDR_DQ2
Data Inputs/Output:
F 3
DQSL
I/O
DDR_LDQS
Data Strobe:
F 7
DQL1
I/O
DDR_DQ1
Data Inputs/Output:
F 8
DQL3
I/O
DDR_DQ3
Data Inputs/Output:
F 9
VSSQ
G
DG
G 1
VSSQ
G
DG
G 2
DQL6
I/O
DDR_DQ6
Data Inputs/Output:
G 3
/DQSL
I/O
DDR_*LDQS
Data Strobe:
G 7
VDD
P
1.5V
G 8
VSS
G
DG
G 9
VSSQ
G
DG
H 1
VREFDQ
I
VREFDQ
Reference voltage for DQ
H 2
VDDQ
P
1.5V
H 3
DQL4
I/O
DDR_DQ4
Data Inputs/Output:
H 7
DQL7
I/O
DDR_DQ7
Data Inputs/Output:
H 8
DQL5
I/O
DDR_DQ5
Data Inputs/Output:
H 9
VDDQ
P
1.5V
J 1
NC
-
-
-
J 2
VSS
G
DG
J 3
/RAS
I
DDR_RAS
Command Inputs:
J 7
CK
I
DDR_CK
Clock
J 8
VSS
G
DG
J 9
NC
-
-
-
K 1
ODT
I
DDR_ODT
On Die Termination:
K 2
VDD
P
1.5V
K 3
/CAS
I
DDR_CAS
Command Inputs:
K 7
/CK
I
DDR_*CK
Complement Clock
K 8
VDD
P
1.5V
K 9
CKE
I
DDR_CKE
Clock Enable:
L 1
NC
-
-
-
L 2
/CS
I
DDR_*CS0
Chip Select:
L 3
/WE
I
DDR_WE
Command Inputs:
88
KX-TGP600RUB/KX-TPA60RUB
L 7
A10/AP
I
DDR_DA10
address/Auto-Precharge
L 8
ZQ
P
ZQ
Pull down via R100
Reference pin for ZQ calibration.
L 9
NC
-
-
-
M 1
VSS
G
DG
M 2
BA0
I
DDR_BA0
Bank Address
M 3
BA2
I
DDR_BA2
Bank Address
M 7
NC
-
-
M 8
VREFCA
I
VREFCA
Reference voltage for CA
M 9
VSS
G
DG
N 1
VDD
P
1.5V
N 2
A3
I
DDR_DA3
address
N 3
A0
I
DDR_DA0
address
N 7
A12/BC
I
DDR_DA12
DDR_DA12
address/Burst Chop:
N 8
BA1
I
DDR_BA1
Bank Address
N 9
VDD
P
1.5V
P 1
VSS
G
DG
P 2
A5
I
DDR_DA5
address
P 3
A2
I
DDR_DA2
address
P 7
A1
I
DDR_DA1
address
P 8
A4
I
DDR_DA4
address
P 9
VSS
G
DG
R 1
VDD
P
1.5V
R 2
A7
I
DDR_DA7
address
R 3
A9
I
DDR_DA9
address
R 7
A11
I
DDR_DA11
address
R 8
A6
I
DDR_DA6
address
R 9
VDD
P
1.5V
T 1
VSS
G
DG
T 2
/RESET
I
DDRRST
Active Low Asynchronous Reset:
T 3
NC
-
DDR_DA13
-
no conection
T 7
NC
-
DDR_DA14
-
no conection
T 8
A8
I
DDR_DA8
address
T 9
VSS
G
DG
Pin No.
Terminal Name
I/O setting
Contens of Control
Pull-up/down
Processing
Remark
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