Panasonic KX-TGP600RUB / KX-TPA60RUB Service Manual ▷ View online
81
KX-TGP600RUB/KX-TPA60RUB
17 Exploded View and Replacement Parts List
17.1. IC Data (Base Unit)
17.1.1.
IC101 (DVF)
Pin
No.
No.
Terminal Name
I/O setting
Contens of
Control
Pull-up/down Processing
Remark
A 1
GND
G
DG
A 2
MEMXA2_EXTINT4
-
-
-
-
A 3
MEMXA3_LCDGP0
-
-
-
-
A 4
DDR_REF2
I
DDR_REF2
DDR Reference Voltage Input
A 5
DDRDQS1_N
I/O
DDRD_/UDQS
DDR Data Strobe 1 Negative
A 6
DDRDQS1
I/O
DDR_/UQS1
DDR Data Strobe 1 Positive
A 7
DDRDQ0
I/O
DDR_DQ0
DDR Data
A 8
DDRDQS0_N
I/O
DDR_/LDQS
DDR Data Strobe 0 Negative
A 9
DDRDQS0
I/O
DDR_LDQS
DDR Data Strobe 0 Positive
A10
DDRDQ5
I/O
DDR_DQ5
DDR Data
A11
DDR_REF1
I
DDR_REF1
DDR Reference Voltage Input
A12
DDRODT0
O
DDRODT0
Pull Down via R107
DDR On-Die Termination
A13
DDRCKELP
-
-
-
-
A14
DDRWE_N
O
DDR_/WE
DDR Write Enable Active Low
A15
DDRCLK1
-
-
-
-
A16
DDRCLK1_N
-
-
-
-
A17
DDRCLK0
O
DDR_CK
DDR Diff Clock 0 Positive
A18
DDRCLK0_N
O
DDR_/CK
DDR Diff Clock 0 Negative
A19
DDRA7
O
DDR_DA7
DDR Command/Address Bus
B 1
MEMXA0_LCDD22
O
DCX_RST1
B 2
MEMXA4_LCDGP1
-
-
-
-
B 3
MEMXA1_LCDD23
-
-
-
-
B 4
DDRDQ8
I/O
DDR_DQ8
DDR Data
B 5
DDRDQ11
I/O
DDR_DQ11
DDR Data
B 6
DDRDM1
O
DDR_*UDM
DDR Data Mask
B 7
DDRDQ1
I/O
DDR_DQ1
DDR Data
B 8
DDRDQ2
I/O
DDR_DQ2
DDR Data
B 9
DDRDQ4
I/O
DDR_DQ4
DDR Data
B10
DDRDQ7
I/O
DDR_DQ7
DDR Data
B11
DDRCS1
-
-
-
-
B12
DDRCAS_N
O
DDR_/CAS
DDR Column Select Active Low
B13
DDRRAS_N
O
DDR_/RAS
DDR Row Select Active Low
B14
DDRBA1
O
DDR_BA1
DDR Bank Address Bus
B15
DDRA0
O
DDR_DA0
DDR Command/Address Bus
B16
DDRA3
O
DDR_DA3
DDR Command/Address Bus
B17
DDRA6
O
DDR_DA6
DDR Command/Address Bus
B18
DDRA10
O
DDR_A10
DDR Command/Address Bus
B19
DDRA14
-
-
-
-
C 1
MEMXA6_LCDGP3
-
-
-
-
C 2
MEMXA10_LCDGP7
-
-
-
-
C 3
MEMXA5_LCDGP2
-
-
-
-
C 4
DDR_RTT
I
DDR_RTT
Pull Down via R 116
DDR Receiver Termination Compensation
C 5
DDRDQ10
I/O
DDR_DQ10
DDR Data
C 6
DDRDQ12
I/O
DDR_DQ12
DDR Data
C 7
DDRDQ14
I/O
DDR_DQ14
DDR Data
C 8
DDRDQ3
I/O
DDR_DQ3
DDR Data
C 9
DDRDQ6
I/O
DDR_DQ6
DDR Data
C10
DDRCS0
O DDR_/CS0
DDR
CS
C11
DDRODT1
-
-
-
-
C12
DDRA1
O
DDR_DA1
DDR Command/Address Bus
C13
DDRBA2
O
DDR_BA2
DDR Bank Address Bus
C14
DDRA2
O
DDR_DA2
DDR Command/Address Bus
C15
DDRA5
O
DDR_DA5
DDR Command/Address Bus
C16
DDRA8
O
DDR_DA8
DDR Command/Address Bus
C17
DDRA12
O
DDR_DA12
DDR Command/Address Bus
C18
DDR_REF0
I
DDR_REF0
DDR Reference Voltage Input
C19
SPI2DO
-
-
-
-
D 1
MEMXA13_BA0_LCDD1
-
-
-
-
82
KX-TGP600RUB/KX-TPA60RUB
D 2
DD1
-
-
-
-
D 3
MEMXA7_LCDGP4
-
-
-
-
D 4
MEMXA14_BA1_LCDD8
-
-
-
-
D 5
MEMXA16 DDRDQ9
I/O
DDR_DQ9
DDR Data
D 6
DDRDQ13
I/O
DDR_DQ13
DDR Data
D 7
DDRDQ15
I/O
DDR_DQ15
DDR Data
D 8
DDRDM0
O
DDR_LDM
DDR Data Mask
D 9
DDRRST_N
O
DDRRST
DDR Reset Active Low
D10
DDRCKE
O
DDR_CKE
DDR Clock Enable
D11
DDRBA0
O
DDR_BA0
DDR Bank Address Bus
D12
VDD
P
1.3VDD
D13
DDRA4
O
DDR_DA4
DDR Command/Address Bus
D14
DDRA9
O
DDR_DA9
DDR Command/Address Bus
D15
DDRA11
O
DDR_DA11
DDR Command/Address Bus
D16
DDRA13
-
-
-
-
D17
SPI2DI
-
-
-
-
D18
SPI2CK
-
-
-
-
D19
D1RX
I
TDMA_RXD
TDMI RX DATA
E 1
MEMXA20_MEMRAS_LCD
D16
D16
-
-
-
-
E 2
MEMXA9_LCDGP6
-
-
-
-
E 3
MEMXA8_LCDGP5
-
-
-
-
E 4
MEMRD
-
-
-
-
E 5
VDD
P
1.3VDD
E 6
VDD
P
1.3VDD
E 7
VDDIO_DDR
P
1.5V
E 8
VDD
P
1.3VDD
E 9
GND
G
DG
E10
VDDIO_DDR
P
1.5V
E11
PLL2_DVDD
P
1.3VDD
VDD
E12
E_VDDQ
-
-
-
-
E13
PLL1_DVDD
P
1.3VDD
VDD
E14
DDRPADLO
I
DDRPADLO
PULL UP via R110
DDR Low Drive Strength
E15
SPI1CK
O
SPI1CK
SPI CLOCK
E16
DDRPADHI
I
DDRPADHI
PULL DOWN via R115
DDR High Drive Strength
E17
SPI1DO
O
SPI1DO
SPI DATA OUT
E18
F1SYNC
I/O
F1SYNC
TDMI FRAME SYNC
E19
XI25M
-
-
-
-
F 1
MEMCKE_EXTINT13
-
-
-
-
F 2
MEMXA19_MEMCAS_LCD
D9
D9
-
-
-
-
F 3
MEMXA11_LCDGP8
-
-
-
-
F 4
MEMXA15
-
-
-
-
F 5
VDDIO_DDR
P
1.5V
F 6
VDDIO_DDR
P
1.5V
F 7
VDDIO_DDR
P
1.5V
F 8
VDDIO_DDR
P
1.5V
F 9
VDDIO_DDR
P
1.5V
F10
VDDIO_DDR
P
1.5V
F11
PLL2_AVDD
P
1.3VDD
VDD
F12
PLL1_AVSS
G
DG
F13
PLL1_AVDD
P
1.3VDD
VDD
F14
SPI1CS0
O
SPI1_CS0
SPI Chip select
F15
D1TX
O
TDMA_TXD
TDM TXDATA
F16
TEST
I
DG
F17
T1SCLK
I/O
TDMA_SCLK
TDMA_SCLK
F18
TRST
I
TRST
F19
XO25M
-
-
-
-
G 1
MEMCLK
-
-
-
-
G 2
MEMXA12_EXTINT14
-
-
-
-
G 3
MEMCS0_LCDD0
-
-
-
-
G 4
MEMCS1_LPCLK
-
-
-
-
G 5
VDDIO
P
3.2V
G 6
GND
G
DG
G 7
GND
G
DG
G 8
GND
G
DG
Pin
No.
No.
Terminal Name
I/O setting
Contens of
Control
Pull-up/down Processing
Remark
83
KX-TGP600RUB/KX-TPA60RUB
G 9
GND
G
DG
G10
GND
G
DG
G11
VDDIO_DDR
P
1.5V
G12
PLL2_AVSS
G
DG
G13
PLL3_DVDD
P
1.3VDD
VDD
G14
SPI1DI
I
SPI1_DI
SPI DATA IN
G15
TCK
I
TCK
G16
TDI
I
TDI
G17
EXTINT15_SYNCPORT
I
DCX1_READY
G18
RF_RADIO_EN_EXTINT9
I
USB_DET
G19
MAIN_CLK_OUT
-
-
-
-
H 1
MEMXD8_LCDD12
I/O
PHY_RST
H 2
MEMDQMBLS0_LCDD17
-
-
-
-
H 3
MEMCS2_EXTINT6
-
-
-
-
H 4
MEMCS3_EXTINT7
-
-
-
-
H 5
VDD
P
1.3VDD
H 6
VDDIO
P
3.2V
H 7
GND
G
DG
H 8
GND
G
DG
H 9
GND
G
DG
H10
GND
G
DG
H11
GND
G
DG
H12
GND
G
DG
H13
PLL3_AVSS
G
DG
H14
ETEST
-
-
-
-
H15
TMS
-
-
-
-
H16
TDO
-
-
-
-
H17
RF_SDATA_IN_SD_D3
-
-
-
-
H18
RF_TR_DATA_EXTINT10
O
DVF_TXREQ
H19
RF_SLOT_CTRL_SD_DET
ECT
ECT
-
-
-
-
J 1
MEMXD9_LCDD13
-
-
-
-
J 2
MEMXD7_LCDD11
-
-
-
-
J 3
MEMDQMBLS1_EXTINT5
-
-
-
-
J 4
MEMWR
-
-
-
-
J 5
VDDIO
P
3.2V
J 6
GND
G
DG
J 7
GND
G
DG
J 8
GND
G
DG
J 9
GND
G
DG
J10
GND
G
DG
J11
GND
G
DG
J12
OSC25M_VSS
G
DG
J13
OSC25M_VDD12
P
1.3VDD
J14
IF_T_DATA
-
-
-
-
J15
IF_RX1
O
DCX1_BOOT
J16
RF_SEN_SD_WR_PROT
-
-
-
-
J17
RF_SCLK_SD_D2
O
DVF_READY
J18
RF_SDATA_OUT_SD_D1
I
DCX1_TXREQ
J19
IF_EN_DA
-
-
-
-
K 1
MEMXD6_LCDD10
-
-
-
-
K 2
MEMXD5_LCDD7
-
-
-
-
K 3
MEMXD10_LCDD14
-
-
-
-
K 4
MEMXD11_LCDD15
-
-
-
-
K 5
VDD
P
1.3VDD
K 6
GND
G
DG
K 7
GND
G
DG
K 8
GND
G
DG
K 9
GND
G
DG
K10
GND
G
DG
K11
GND
G
DG
K12
VDDIO
P
3.2V
K13
VDD
P
1.3VDD
K14
IF_INT_ANA
-
-
-
-
K15
IF_MLSE
-
-
-
-
K16
IF_NARES
-
-
-
-
Pin
No.
No.
Terminal Name
I/O setting
Contens of
Control
Pull-up/down Processing
Remark
84
KX-TGP600RUB/KX-TPA60RUB
K17
IF_DATA_DA
-
-
-
-
K18
AMPOUT0
-
-
-
-
K19
AMPOUT1
-
-
-
-
L 1
MEMXD3_LCDD5
-
-
-
-
L 2
MEMXD13_LCDD19
-
-
-
-
L 3
MEMXD14_LCDD20
-
-
-
-
L 4
MEMXD2_LCDD4
-
-
-
-
L 5
VDDIO_RGMII
P
3.2 V
L 6
VDDIO
P
3.2 V
L 7
GND
G
DG
L 8
GND
G
DG
L 9
GND
G
DG
L10
GND
G
DG
L11
GND
G
DG
L12
GND
G
DG
L13
PLL3_AVDD
P
1.3VDD
VDD
L14
IF_EN_AD
-
-
-
-
L15
IF_DATA_AD
-
-
-
-
L16
IF_CLK_IF
-
-
-
-
L17
AMPOUT2
-
-
-
-
L18
AMPOUT3
-
-
-
-
L19
DIFFIN1P
-
-
-
-
M 1
MEMXD1_LCDD3
-
-
-
-
M 2
MEMXD4_LCDD6
-
-
-
-
M 3
MEMXD15_LCDD21
-
-
-
-
M 4
MEMXD0_LCDD2
I/O
KEY DETECT
M 5
VCC_USB2
P
3.2V
VCC for USB
M 6
VDDL_USB1
P
1.3VDD
VDD for USB
M 7
OSC12M_VSS
G
DG
M 8
VDD
P
1.3VDD
M 9
GND
G
DG
M10
VDD
P
1.3VDD
M11
GND
G
DG
M12
GND
G
DG
M13
VDDIO_APU
P
1.8V_APU
VDD
M14
VDDIO_RFAPU
P
3.2V
M15
VCC_AMP_OUT
P
3.2V
M16
GND_AMP_OUT
G
DG
M17
DIFFIN0N
-
-
-
-
M18
DIFFIN0P
-
-
-
-
M19
DIFFIN1N
-
-
-
-
N 1
MEMXD12_LCDD18
-
-
-
-
N 2
MIIRXER_EXTINT12
I
MII_RXER
Pull down via R233
PHY Recive Error
N 3
MII_TXER_SPI1CS1
-
-
-
-
N 4
MDC
O
MDC
Pull Up via R238 and R239 PHY Management Data Clock
N 5
VDDA_USB1
P
3.2V
VDDA_USB1 (3.2V)
N 6
USB1VRES
I
USB1VRES
USB1 Reference Circuit Input
N 7
OSC12M_VDD12
P
1.3VDD
N 8
VDDIO_NFLQSPI
P
3.2V%
N 9
VDDIOC
P
3.2V
N10
VDDIO
P
3.2V
N11
DGPIO30
-
-
-
-
N12
VDD
P
1.3VDD
N13
VDD_ANA
O(P)
1.8V_APU
VDD 1.8V
N14
MICPWR1
-
-
-
-
N15
SINGIN0
-
-
-
-
N16
VCCA
P
3.2V
VCC 3.2V
N17
GNDA
G
DG
N18
XI13M
I(A)
XI13M
crystal osc (13.824MHz)
N19
BCLK
O
BCLK
13.824MHz output
P 1
MIIRXD1_RGMIIRD1
I
MII_RXD1
PHY Recive Data
P 2
MIIRXD3_RGMIIRD3
I
MII_RXD3
PHY Recive Data
P 3
MIIRXD2_RGMIIRD2
I
MII_RXD2
PHY Recive Data
P 4
MIIRXCRS_U2TX
I
MII_CRS
PHY Carrier Valid at harf duplex
P 5
USB1ID
I
USB1ID
Pull up via R205
USB1 ID
P 6
USB1VBUS
O
VBU
VBUS Enable
Pin
No.
No.
Terminal Name
I/O setting
Contens of
Control
Pull-up/down Processing
Remark
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